[LLVMbugs] [Bug 18881] New: [AArch64] Produce STLXR with unpredictable behavior.
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Tue Feb 18 02:15:09 PST 2014
http://llvm.org/bugs/show_bug.cgi?id=18881
Bug ID: 18881
Summary: [AArch64] Produce STLXR with unpredictable behavior.
Product: new-bugs
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedbugs at nondot.org
Reporter: kevinqindev at gmail.com
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
Created attachment 12081
--> http://llvm.org/bugs/attachment.cgi?id=12081&action=edit
test file to reproduce
With the following command line
$clang --target=aarch64-linux-gnuabi -mfpu=neon -D_GNU_SOURCE
-D__STDC_LIMIT_MACROS -DNDEBUG -O3 -m64 -fomit-frame-pointer AtomicOps.c
We would see failure as below on foundation model,
$./a.out
[ 8592.507973] a.out[1447]: undefined instruction: pc=00000000004005d0
[ 8592.508058] Code: f94007e0 885ffc01 b94007e2 0b020023 (8803fc03)
Illegal instruction
The assembly code in 00000000004005d0 is
4005d0: 8803fc03 stlxr w3, w3, [x0]
Which result is UNPREDICTABLE.
Compiler shouldn't produce unpredictable instructions, so Ws and Wt must be
different registers.
Below is quoted from ARM reference manual:
STLXR <Ws>, <Wt>, [<Xn|SP>{,#0}]
if memop == MemOp_STORE && excl then
if s == t || (pair && s == t2) then
Constraint c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_NONE, Constraint_UNDEF,
Constraint_NOP};
case c of
when Constraint_UNKNOWN rt_unknown = TRUE; // store UNKNOWN value
when Constraint_NONE rt_unknown = FALSE; // store original value
when Constraint_UNDEF UnallocatedEncoding();
when Constraint_NOP EndOfInstruction();
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