[LLVMbugs] [Bug 18872] New: clang crashes on valid code at -O3 in 32-bit mode on x86_64-linux-gnu
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Mon Feb 17 10:09:59 PST 2014
http://llvm.org/bugs/show_bug.cgi?id=18872
Bug ID: 18872
Summary: clang crashes on valid code at -O3 in 32-bit mode on
x86_64-linux-gnu
Product: clang
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: -New Bugs
Assignee: unassignedclangbugs at nondot.org
Reporter: su at cs.ucdavis.edu
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
The current clang trunk crashes when compiling the following testcase at -O3 in
32-bit mode (but not 64-bit mode) on x86_64-linux-gnu.
This is a regression from clang 3.4.
$ clang-trunk -v
clang version 3.5 (trunk 201500)
Target: x86_64-unknown-linux-gnu
Thread model: posix
Found candidate GCC installation: /usr/lib/gcc/i686-linux-gnu/4.8
Found candidate GCC installation: /usr/lib/gcc/i686-linux-gnu/4.8.1
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.4
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.4.6
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.4.7
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.6
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.6.4
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.7
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.7.3
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.8
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.8.1
Selected GCC installation: /usr/lib/gcc/x86_64-linux-gnu/4.8
Candidate multiilb: .;@m64
Candidate multiilb: 32;@m32
Selected multilib: .;@m64
$
$ clang-trunk -m32 -O2 small.c; a.out
$ clang-trunk -m64 -O3 small.c; a.out
$ clang-3.4 -m32 -O3 small.c; a.out
$
$ clang-trunk -m32 -O3 small.c
# In Register Scavenger
# Machine code for function fn1: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP-20]
fi#1: size=4, align=4, at location [SP-24]
fi#2: size=4, align=4, at location [SP-28]
fi#3: size=4, align=4, at location [SP-32]
fi#4: size=4, align=4, at location [SP-36]
fi#5: size=4, align=4, at location [SP-40]
fi#6: size=4, align=4, at location [SP-44]
fi#7: size=4, align=4, at location [SP-48]
fi#8: dead
fi#9: dead
fi#10: dead
fi#11: dead
fi#12: dead
fi#13: dead
fi#14: dead
fi#15: dead
fi#16: dead
fi#17: dead
fi#18: dead
fi#19: dead
fi#20: size=4, align=4, at location [SP-4]
fi#21: size=4, align=4, at location [SP-8]
fi#22: size=4, align=4, at location [SP-12]
fi#23: size=4, align=4, at location [SP-16]
Function Live Ins: %ECX in %vreg41
BB#0: derived from LLVM BB %entry
Live Ins: %ECX %EBP %EBX %EDI %ESI
PUSH32r %EBP<kill>, %ESP<imp-def>, %ESP<imp-use>; flags: FrameSetup
PUSH32r %EBX<kill>, %ESP<imp-def>, %ESP<imp-use>; flags: FrameSetup
PUSH32r %EDI<kill>, %ESP<imp-def>, %ESP<imp-use>; flags: FrameSetup
PUSH32r %ESI<kill>, %ESP<imp-def>, %ESP<imp-use>; flags: FrameSetup
%ESP<def,tied1> = SUB32ri8 %ESP<tied0>, 32, %EFLAGS<imp-def,dead>; flags:
FrameSetup
%ESI<def> = MOV32rm %noreg, 1, %noreg, <ga:@b>, %noreg;
mem:LD4[getelementptr inbounds (%struct.anon* @b, i32 0, i32
0)](align=1)(tbaa=<badref>)
TEST32rr %ESI, %ESI, %EFLAGS<imp-def>
JE_4 <BB#12>, %EFLAGS<imp-use>
Successors according to CFG: BB#12(12) BB#1(20)
BB#1: derived from LLVM BB %for.body.lr.ph
Live Ins: %ECX %ESI
Predecessors according to CFG: BB#0
MOV32mr %ESP, 1, %noreg, 0, %noreg, %ECX<kill>; mem:ST4[FixedStack7]
%ECX<def> = MOV32rm %noreg, 1, %noreg, <ga:@a>, %noreg;
mem:LD4[@a](tbaa=<badref>)
%EDX<def> = MOV32ri 1
%EDX<def,tied1> = SHL32rCL %EDX<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%EDX<def,tied1> = SHL32ri %EDX<kill,tied0>, 20, %EFLAGS<imp-def,dead>
%EDX<def,tied1> = SAR32ri %EDX<kill,tied0>, 20, %EFLAGS<imp-def,dead>
TEST32rr %ECX<kill>, %ECX, %EFLAGS<imp-def>
%EAX<def> = MOVZX32rm8 %noreg, 1, %noreg, <ga:@d+8>, %noreg;
mem:LD1[bitcast (%struct.S0* @d to i72*)+8]
%EDI<def> = MOV32rm %noreg, 1, %noreg, <ga:@d+4>, %noreg; mem:LD4[bitcast
(%struct.S0* @d to i72*)+4](align=1)
%EBX<def> = MOV32rm %noreg, 1, %noreg, <ga:@d>, %noreg; mem:LD4[bitcast
(%struct.S0* @d to i72*)](align=1)
JE_4 <BB#5>, %EFLAGS<imp-use>
Successors according to CFG: BB#5(12) BB#2(20)
BB#2: derived from LLVM BB %for.body.lr.ph.for.body.lr.ph.split_crit_edge
Live Ins: %EDX %EDI %EAX %EBX %ESI
Predecessors according to CFG: BB#1
TEST32rr %EDX<kill>, %EDX, %EFLAGS<imp-def>
JE_4 <BB#4>, %EFLAGS<imp-use>
Successors according to CFG: BB#4(12) BB#3(20)
BB#3: derived from LLVM BB %for.inc.preheader
Live Ins: %EDI %EAX %EBX %ESI
Predecessors according to CFG: BB#2
%ESI<def,tied1> = DEC32r %ESI<kill,tied0>, %EFLAGS<imp-def,dead>
%EDX<def> = COPY %EDI<kill>
JMP_4 <BB#10>
Successors according to CFG: BB#10
BB#4: derived from LLVM BB %for.inc.us35.preheader
Live Ins: %EDI %EAX %EBX %ESI
Predecessors according to CFG: BB#2
%ESI<def,tied1> = DEC32r %ESI<kill,tied0>, %EFLAGS<imp-def,dead>
%EDX<def> = COPY %EDI<kill>
JMP_4 <BB#8>
Successors according to CFG: BB#8
BB#5: derived from LLVM BB %for.body.lr.ph.split.us
Live Ins: %EDX %EDI %EAX %EBX %ESI
Predecessors according to CFG: BB#1
TEST32rr %EDX<kill>, %EDX, %EFLAGS<imp-def>
JE_4 <BB#9>, %EFLAGS<imp-use>
Successors according to CFG: BB#9(12) BB#6(20)
BB#6: derived from LLVM BB %for.inc.us.preheader
Live Ins: %EDI %EAX %EBX %ESI
Predecessors according to CFG: BB#5
%ESI<def,tied1> = DEC32r %ESI<kill,tied0>, %EFLAGS<imp-def,dead>
%EDX<def> = COPY %EDI<kill>
Successors according to CFG: BB#7
BB#7: derived from LLVM BB %for.inc.us
Live Ins: %EDX %EAX %EBX %ESI
Predecessors according to CFG: BB#6 BB#7
MOV32mr %ESP, 1, %noreg, 24, %noreg, %EDX; mem:ST4[FixedStack1]
MOV32mr %ESP, 1, %noreg, 20, %noreg, %ESI<kill>; mem:ST4[FixedStack2]
MOV32mr %ESP, 1, %noreg, 28, %noreg, %EBX<kill>; mem:ST4[FixedStack0]
%CL<def> = MOV8ri 64
%EBX<def> = MOV32ri 48
%CL<def,tied1> = SUB8rr %CL<kill,tied0>, %BL, %EFLAGS<imp-def,dead>,
%EBX<imp-use,kill>
MOV8mr %ESP, 1, %noreg, 8, %noreg, %CL; mem:ST1[FixedStack5]
%EBP<def> = MOVZX32rr8 %AL
%EBX<def> = COPY %EBP
%EBX<def,tied1> = SHL32rCL %EBX<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %CL<kill>, 32, %EFLAGS<imp-def>
%ESI<def> = MOV32ri 0
%EBX<def,tied1> = CMOVNE32rr %EBX<kill,tied0>, %ESI<kill>, %EFLAGS<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDI<def> = MOV32rm %ESP, 1, %noreg, 28, %noreg; mem:LD4[FixedStack0]
%EDI<def,tied1> = SHRD32rrCL %EDI<kill,tied0>, %EDX, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%ESI<def> = COPY %EDX<kill>
%ESI<def,tied1> = SHR32rCL %ESI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>
%ESI<def,tied1> = CMOVE32rr %ESI<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
%EDI<def> = MOVZX32rr8 %CL, %ECX<imp-use,kill>
MOV32mr %ESP, 1, %noreg, 12, %noreg, %EDI; mem:ST4[FixedStack4]
%ECX<def> = MOV32ri 0
%ECX<def,tied1> = CMOVNE32rr %ECX<kill,tied0>, %ECX, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 4, %noreg, %ECX<kill>; mem:ST4[FixedStack6]
%ESI<def,tied1> = OR32rr %ESI<kill,tied0>, %EBX<kill>,
%EFLAGS<imp-def,dead>
%EBX<def> = MOV32ri 48
%BL<def,tied1> = ADD8ri %BL<tied0>, -64, %EFLAGS<imp-def,dead>,
%EBX<imp-use,kill>, %EBX<imp-def>
%CL<def> = COPY %BL
%EDX<def> = MOV32ri 0
%EBP<def,tied1> = SHRD32rrCL %EBP<kill,tied0>, %EDX, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %BL, 32, %EFLAGS<imp-def>
%EBP<def,tied1> = CMOVNE32rr %EBP<kill,tied0>, %EDX<kill>, %EFLAGS<imp-use>
CMP32ri8 %EDI<kill>, 64, %EFLAGS<imp-def>
%EBP<def,tied1> = CMOVB32rr %EBP<kill,tied0>, %ESI<kill>, %EFLAGS<imp-use>
%EBP<def,tied1> = AND32ri %EBP<kill,tied0>, 4194303, %EFLAGS<imp-def,dead>
%EBP<def,tied1> = XOR32ri8 %EBP<kill,tied0>, 1, %EFLAGS<imp-def,dead>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%ESI<def> = COPY %EBP
%ESI<def,tied1> = SHL32rCL %ESI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%ECX<def> = COPY %ESI
%EDI<def> = MOV32ri 0
%ECX<def,tied1> = CMOVNE32rr %ECX<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[FixedStack3]
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
%EDX<def,tied1> = SHLD32rrCL %EDX<kill,tied0>, %EBP, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%EDX<def,tied1> = CMOVNE32rr %EDX<kill,tied0>, %ESI<kill>, %EFLAGS<imp-use>
%ESI<def> = COPY %EBP
CMP32mi8 %ESP, 1, %noreg, 12, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack4]
%ECX<def> = MOV32ri 0
%EDX<def,tied1> = CMOVAE32rr %EDX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%ECX<def> = MOV32rm %ESP, 1, %noreg, 16, %noreg; mem:LD4[FixedStack3]
%EDI<def> = MOV32ri 0
%ECX<def,tied1> = CMOVAE32rr %ECX<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 16, %noreg, %ECX<kill>; mem:ST4[FixedStack3]
%CL<def> = COPY %BL
%ESI<def,tied1> = SHL32rCL %ESI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %BL, 32, %EFLAGS<imp-def>, %EBX<imp-use,kill>
%EBX<def> = MOV32rm %ESP, 1, %noreg, 28, %noreg; mem:LD4[FixedStack0]
%ECX<def> = MOV32ri 0
%ESI<def,tied1> = CMOVNE32rr %ESI<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%EDI<def> = MOV32ri 0
%CL<def> = MOV8rm %ESP, 1, %noreg, 8, %noreg; mem:LD1[FixedStack5]
%EBP<def,tied1> = SHRD32rrCL %EBP<kill,tied0>, %EDI<kill>,
%EFLAGS<imp-def,dead>, %CL<imp-use>
%EDI<def> = MOV32ri 0
TEST8ri %CL<kill>, 32, %EFLAGS<imp-def>
%EBP<def,tied1> = CMOVNE32rr %EBP<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
%EBP<def,tied1> = OR32rm %EBP<kill,tied0>, %ESP, 1, %noreg, 4, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack6]
CMP32mi8 %ESP, 1, %noreg, 12, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack4]
%EBP<def,tied1> = CMOVAE32rr %EBP<kill,tied0>, %ESI<kill>, %EFLAGS<imp-use>
%ESI<def> = MOV32rm %ESP, 1, %noreg, 20, %noreg; mem:LD4[FixedStack2]
%ECX<def> = MOV32ri 65535
AND32mr %ESP, 1, %noreg, 24, %noreg, %ECX<kill>, %EFLAGS<imp-def,dead>;
mem:ST4[FixedStack1]
OR32mr %ESP, 1, %noreg, 24, %noreg, %EDX<kill>, %EFLAGS<imp-def,dead>;
mem:ST4[FixedStack1]
%EDX<def> = MOV32rm %ESP, 1, %noreg, 24, %noreg; mem:LD4[FixedStack1]
%ECX<def> = MOV32ri 192
%EAX<def,tied1> = AND32rr %EAX<kill,tied0>, %ECX<kill>,
%EFLAGS<imp-def,dead>
%EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EBP<kill>,
%EFLAGS<imp-def,dead>
%ECX<def> = MOV32ri -1
%EBX<def,tied1> = AND32rr %EBX<kill,tied0>, %ECX<kill>,
%EFLAGS<imp-def,dead>
%EBX<def,tied1> = OR32rm %EBX<kill,tied0>, %ESP, 1, %noreg, 16, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack3]
%EAX<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
MOV32mr %noreg, 1, %noreg, <ga:@b>, %noreg, %ESI; mem:ST4[getelementptr
inbounds (%struct.anon* @b, i32 0, i32 0)](align=1)(tbaa=<badref>)
%ESI<def,tied1> = DEC32r %ESI<kill,tied0>, %EFLAGS<imp-def,dead>
CMP32ri8 %ESI, -1, %EFLAGS<imp-def>
JNE_4 <BB#7>, %EFLAGS<imp-use>
JMP_4 <BB#11>
Successors according to CFG: BB#11(4) BB#7(124)
BB#8: derived from LLVM BB %for.inc.us35
Live Ins: %EDX %EAX %EBX %ESI
Predecessors according to CFG: BB#4 BB#8
MOV32mr %ESP, 1, %noreg, 24, %noreg, %EDX; mem:ST4[FixedStack1]
MOV32mr %ESP, 1, %noreg, 20, %noreg, %ESI<kill>; mem:ST4[FixedStack2]
MOV32mr %ESP, 1, %noreg, 28, %noreg, %EBX<kill>; mem:ST4[FixedStack0]
%CL<def> = MOV8ri 64
%EBX<def> = MOV32ri 48
%CL<def,tied1> = SUB8rr %CL<kill,tied0>, %BL, %EFLAGS<imp-def,dead>,
%EBX<imp-use,kill>
MOV8mr %ESP, 1, %noreg, 4, %noreg, %CL; mem:ST1[FixedStack6]
%ESI<def> = MOVZX32rr8 %AL
%EDI<def> = COPY %ESI
%EDI<def,tied1> = SHL32rCL %EDI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %CL<kill>, 32, %EFLAGS<imp-def>
%EBX<def> = MOV32ri 0
%EDI<def,tied1> = CMOVNE32rr %EDI<kill,tied0>, %EBX<kill>, %EFLAGS<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EBX<def> = MOV32rm %ESP, 1, %noreg, 28, %noreg; mem:LD4[FixedStack0]
%EBX<def,tied1> = SHRD32rrCL %EBX<kill,tied0>, %EDX, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EBP<def> = COPY %EDX<kill>
%EBP<def,tied1> = SHR32rCL %EBP<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>
%EBP<def,tied1> = CMOVE32rr %EBP<kill,tied0>, %EBX<kill>, %EFLAGS<imp-use>
%EBX<def> = MOVZX32rr8 %CL, %ECX<imp-use,kill>
MOV32mr %ESP, 1, %noreg, 16, %noreg, %EBX<kill>; mem:ST4[FixedStack3]
%EBX<def> = MOV32ri 0
%EBX<def,tied1> = CMOVNE32rr %EBX<kill,tied0>, %EBX, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 8, %noreg, %EBX<kill>; mem:ST4[FixedStack5]
%EBP<def,tied1> = OR32rr %EBP<kill,tied0>, %EDI<kill>,
%EFLAGS<imp-def,dead>
%EBX<def> = MOV32ri 48
%BL<def,tied1> = ADD8ri %BL<tied0>, -64, %EFLAGS<imp-def,dead>,
%EBX<imp-use,kill>, %EBX<imp-def>
%CL<def> = COPY %BL
%EDI<def> = MOV32ri 0
%ESI<def,tied1> = SHRD32rrCL %ESI<kill,tied0>, %EDI, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %BL, 32, %EFLAGS<imp-def>
%ESI<def,tied1> = CMOVNE32rr %ESI<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
CMP32mi8 %ESP, 1, %noreg, 16, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack3]
%ESI<def,tied1> = CMOVB32rr %ESI<kill,tied0>, %EBP<kill>, %EFLAGS<imp-use>
%ESI<def,tied1> = AND32ri %ESI<kill,tied0>, 4194303, %EFLAGS<imp-def,dead>
%ESI<def,tied1> = XOR32ri8 %ESI<kill,tied0>, 1, %EFLAGS<imp-def,dead>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDI<def> = COPY %ESI
%EDI<def,tied1> = SHL32rCL %EDI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%EBP<def> = COPY %EDI
%ECX<def> = MOV32ri 0
%EBP<def,tied1> = CMOVNE32rr %EBP<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 12, %noreg, %EBP<kill>; mem:ST4[FixedStack4]
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
%EDX<def,tied1> = SHLD32rrCL %EDX<kill,tied0>, %ESI, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%EDX<def,tied1> = CMOVNE32rr %EDX<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
%EDI<def> = COPY %ESI
CMP32mi8 %ESP, 1, %noreg, 16, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack3]
%ECX<def> = MOV32ri 0
%EDX<def,tied1> = CMOVAE32rr %EDX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%ECX<def> = MOV32rm %ESP, 1, %noreg, 12, %noreg; mem:LD4[FixedStack4]
%EBP<def> = MOV32ri 0
%ECX<def,tied1> = CMOVAE32rr %ECX<kill,tied0>, %EBP<kill>, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 12, %noreg, %ECX<kill>; mem:ST4[FixedStack4]
%CL<def> = COPY %BL
%EDI<def,tied1> = SHL32rCL %EDI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %BL, 32, %EFLAGS<imp-def>, %EBX<imp-use,kill>
%EBX<def> = MOV32rm %ESP, 1, %noreg, 28, %noreg; mem:LD4[FixedStack0]
%ECX<def> = MOV32ri 0
%EDI<def,tied1> = CMOVNE32rr %EDI<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%EBP<def> = MOV32ri 0
%CL<def> = MOV8rm %ESP, 1, %noreg, 4, %noreg; mem:LD1[FixedStack6]
%ESI<def,tied1> = SHRD32rrCL %ESI<kill,tied0>, %EBP<kill>,
%EFLAGS<imp-def,dead>, %CL<imp-use>
%EBP<def> = MOV32ri 0
TEST8ri %CL<kill>, 32, %EFLAGS<imp-def>
%ESI<def,tied1> = CMOVNE32rr %ESI<kill,tied0>, %EBP<kill>, %EFLAGS<imp-use>
%ESI<def,tied1> = OR32rm %ESI<kill,tied0>, %ESP, 1, %noreg, 8, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack5]
CMP32mi8 %ESP, 1, %noreg, 16, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack3]
%ESI<def,tied1> = CMOVAE32rr %ESI<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
%ECX<def> = MOV32ri 65535
AND32mr %ESP, 1, %noreg, 24, %noreg, %ECX<kill>, %EFLAGS<imp-def,dead>;
mem:ST4[FixedStack1]
OR32mr %ESP, 1, %noreg, 24, %noreg, %EDX<kill>, %EFLAGS<imp-def,dead>;
mem:ST4[FixedStack1]
%EDX<def> = MOV32rm %ESP, 1, %noreg, 24, %noreg; mem:LD4[FixedStack1]
%ECX<def> = MOV32ri 192
%EAX<def,tied1> = AND32rr %EAX<kill,tied0>, %ECX<kill>,
%EFLAGS<imp-def,dead>
%EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %ESI<kill>,
%EFLAGS<imp-def,dead>
%ESI<def> = MOV32rm %ESP, 1, %noreg, 20, %noreg; mem:LD4[FixedStack2]
%ECX<def> = MOV32ri -1
%EBX<def,tied1> = AND32rr %EBX<kill,tied0>, %ECX<kill>,
%EFLAGS<imp-def,dead>
%EBX<def,tied1> = OR32rm %EBX<kill,tied0>, %ESP, 1, %noreg, 12, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack4]
%EAX<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
MOV32mr %noreg, 1, %noreg, <ga:@b>, %noreg, %ESI; mem:ST4[getelementptr
inbounds (%struct.anon* @b, i32 0, i32 0)](align=1)(tbaa=<badref>)
%ESI<def,tied1> = DEC32r %ESI<kill,tied0>, %EFLAGS<imp-def,dead>
CMP32ri8 %ESI, -1, %EFLAGS<imp-def>
JNE_4 <BB#8>, %EFLAGS<imp-use>
JMP_4 <BB#11>
Successors according to CFG: BB#11(4) BB#8(124)
BB#9: derived from LLVM BB %if.then
Live Ins: %EDI %EAX %EBX
Predecessors according to CFG: BB#5
%CH<def> = MOV8ri 64
%ESI<def> = COPY %EAX
%EDX<def> = MOV32ri 48
%CH<def,tied1> = SUB8rr %CH<kill,tied0>, %DL, %EFLAGS<imp-def,dead>,
%EDX<imp-use,kill>
MOV8mr %ESP, 1, %noreg, 16, %noreg, %CH; mem:ST1[FixedStack3]
%CL<def> = COPY %CH
%ESI<def,tied1> = SHL32rCL %ESI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
%EBP<def> = COPY %EBX
TEST8ri %CH<kill>, 32, %EFLAGS<imp-def>
%ESI<def,tied1> = CMOVNE32rr %ESI<kill,tied0>, %EDX<kill>, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 24, %noreg, %EDI; mem:ST4[FixedStack1]
%EBP<def,tied1> = SHRD32rrCL %EBP<kill,tied0>, %EDI, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDX<def> = MOV32ri 48
%EDX<def> = MOVZX32rr8 %DL, %EDX<imp-use,kill>
MOV32mr %ESP, 1, %noreg, 20, %noreg, %EDX<kill>; mem:ST4[FixedStack2]
%EDX<def> = COPY %EAX
MOV32mr %ESP, 1, %noreg, 28, %noreg, %EBX<kill>; mem:ST4[FixedStack0]
%EBX<def> = MOV32ri 48
%EDI<def,tied1> = SHR32rCL %EDI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%EDI<def,tied1> = CMOVE32rr %EDI<kill,tied0>, %EBP<kill>, %EFLAGS<imp-use>
%ECX<def> = MOV32ri 0
%ECX<def,tied1> = CMOVNE32rr %ECX<kill,tied0>, %ECX, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 12, %noreg, %ECX<kill>; mem:ST4[FixedStack4]
%BL<def,tied1> = ADD8ri %BL<tied0>, -64, %EFLAGS<imp-def,dead>,
%EBX<imp-use,kill>, %EBX<imp-def>
%CL<def> = COPY %BL
%EBP<def> = MOV32r0 %EFLAGS<imp-def,dead>
%EDX<def,tied1> = SHRD32rrCL %EDX<kill,tied0>, %EBP, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%EDI<def,tied1> = OR32rr %EDI<kill,tied0>, %ESI<kill>,
%EFLAGS<imp-def,dead>
TEST8ri %BL, 32, %EFLAGS<imp-def>
%EDX<def,tied1> = CMOVNE32rr %EDX<kill,tied0>, %EBP<kill>, %EFLAGS<imp-use>
CMP32mi8 %ESP, 1, %noreg, 20, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack2]
%EDX<def,tied1> = CMOVB32rr %EDX<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
%EDX<def,tied1> = AND32ri %EDX<kill,tied0>, 4194303, %EFLAGS<imp-def,dead>
%EDX<def,tied1> = XOR32ri8 %EDX<kill,tied0>, 1, %EFLAGS<imp-def,dead>
%ESI<def> = COPY %EDX
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%ESI<def,tied1> = SHL32rCL %ESI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%EBP<def> = COPY %ESI
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%ECX<def> = MOV32ri 0
%EBP<def,tied1> = CMOVNE32rr %EBP<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%EDI<def> = MOV32r0 %EFLAGS<imp-def,dead>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDI<def,tied1> = SHLD32rrCL %EDI<kill,tied0>, %EDX, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%EDI<def,tied1> = CMOVNE32rr %EDI<kill,tied0>, %ESI<kill>, %EFLAGS<imp-use>
%ESI<def> = COPY %EDX
CMP32mi8 %ESP, 1, %noreg, 20, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack2]
%ECX<def> = MOV32ri 0
%EBP<def,tied1> = CMOVAE32rr %EBP<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%CL<def> = COPY %BL
%ESI<def,tied1> = SHL32rCL %ESI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %BL, 32, %EFLAGS<imp-def>, %EBX<imp-use,kill>
%EBX<def> = MOV32ri 0
%ESI<def,tied1> = CMOVNE32rr %ESI<kill,tied0>, %EBX, %EFLAGS<imp-use>
%CL<def> = MOV8rm %ESP, 1, %noreg, 16, %noreg; mem:LD1[FixedStack3]
%EDX<def,tied1> = SHRD32rrCL %EDX<kill,tied0>, %EBX<kill>,
%EFLAGS<imp-def,dead>, %CL<imp-use>
TEST8ri %CL<kill>, 32, %EFLAGS<imp-def>
%ECX<def> = MOV32ri 0
%EDX<def,tied1> = CMOVNE32rr %EDX<kill,tied0>, %ECX, %EFLAGS<imp-use>
%EDX<def,tied1> = OR32rm %EDX<kill,tied0>, %ESP, 1, %noreg, 12, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack4]
CMP32mi8 %ESP, 1, %noreg, 20, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack2]
%EDI<def,tied1> = CMOVAE32rr %EDI<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%EDX<def,tied1> = CMOVAE32rr %EDX<kill,tied0>, %ESI<kill>, %EFLAGS<imp-use>
%ECX<def> = MOV32ri 192
%ECX<def,tied1> = AND32rr %ECX<kill,tied0>, %EAX<kill>,
%EFLAGS<imp-def,dead>
%EAX<def> = MOV32ri -1
%EAX<def,tied1> = AND32rm %EAX<kill,tied0>, %ESP, 1, %noreg, 28, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack0]
%ESI<def> = MOV32ri 65535
%ESI<def,tied1> = AND32rm %ESI<kill,tied0>, %ESP, 1, %noreg, 24, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack1]
%ECX<def,tied1> = OR32rr %ECX<kill,tied0>, %EDX<kill>,
%EFLAGS<imp-def,dead>
%ESI<def,tied1> = OR32rr %ESI<kill,tied0>, %EDI<kill>,
%EFLAGS<imp-def,dead>
%EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EBP<kill>,
%EFLAGS<imp-def,dead>
MOV32mr %noreg, 1, %noreg, <ga:@d+4>, %noreg, %ESI<kill>; mem:ST4[bitcast
(%struct.S0* @d to i72*)+4](align=1)
MOV32mr %noreg, 1, %noreg, <ga:@d>, %noreg, %EAX<kill>; mem:ST4[bitcast
(%struct.S0* @d to i72*)](align=1)
MOV8mr %noreg, 1, %noreg, <ga:@d+8>, %noreg, %CL, %ECX<imp-use,kill>;
mem:ST1[bitcast (%struct.S0* @d to i72*)+8]
%EAX<def> = MOV32rm %noreg, 1, %noreg, <ga:@e>, %noreg;
mem:LD4[getelementptr inbounds (%struct.S1* @e, i32 0, i32
0)](align=1)(tbaa=<badref>)
%ECX<def> = MOV32rm %ESP, 1, %noreg, 0, %noreg; mem:LD4[FixedStack7]
JMP_4 <BB#14>
Successors according to CFG: BB#14
BB#10: derived from LLVM BB %for.inc
Live Ins: %EDX %EAX %EBX %ESI
Predecessors according to CFG: BB#3 BB#10
MOV32mr %ESP, 1, %noreg, 20, %noreg, %ESI<kill>; mem:ST4[FixedStack2]
MOV32mr %ESP, 1, %noreg, 28, %noreg, %EBX<kill>; mem:ST4[FixedStack0]
MOV32mr %ESP, 1, %noreg, 16, %noreg, %EAX; mem:ST4[FixedStack3]
%CL<def> = MOV8ri 64
%EBX<def> = MOV32ri 48
%CL<def,tied1> = SUB8rr %CL<kill,tied0>, %BL, %EFLAGS<imp-def,dead>,
%EBX<imp-use,kill>
MOV8mr %ESP, 1, %noreg, 8, %noreg, %CL; mem:ST1[FixedStack5]
%ESI<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
%EDI<def> = COPY %ESI
%EDI<def,tied1> = SHL32rCL %EDI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %CL<kill>, 32, %EFLAGS<imp-def>
%EAX<def> = MOV32ri 0
%EDI<def,tied1> = CMOVNE32rr %EDI<kill,tied0>, %EAX<kill>, %EFLAGS<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EBX<def> = MOV32rm %ESP, 1, %noreg, 28, %noreg; mem:LD4[FixedStack0]
%EBX<def,tied1> = SHRD32rrCL %EBX<kill,tied0>, %EDX, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EBP<def> = COPY %EDX
%EBP<def,tied1> = SHR32rCL %EBP<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%EAX<def> = MOV32ri 48
TEST8ri %AL, 32, %EFLAGS<imp-def>
%EBP<def,tied1> = CMOVE32rr %EBP<kill,tied0>, %EBX<kill>, %EFLAGS<imp-use>
%EAX<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
MOV32mr %ESP, 1, %noreg, 24, %noreg, %EAX; mem:ST4[FixedStack1]
%EBX<def> = MOV32ri 0
%EBX<def,tied1> = CMOVNE32rr %EBX<kill,tied0>, %EBX, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 12, %noreg, %EBX<kill>; mem:ST4[FixedStack4]
%EBP<def,tied1> = OR32rr %EBP<kill,tied0>, %EDI<kill>,
%EFLAGS<imp-def,dead>
%EBX<def> = MOV32ri 48
%BL<def,tied1> = ADD8ri %BL<tied0>, -64, %EFLAGS<imp-def,dead>,
%EBX<imp-use,kill>, %EBX<imp-def>
%CL<def> = COPY %BL
%EDI<def> = MOV32ri 0
%ESI<def,tied1> = SHRD32rrCL %ESI<kill,tied0>, %EDI, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %BL, 32, %EFLAGS<imp-def>
%ESI<def,tied1> = CMOVNE32rr %ESI<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
CMP32ri8 %EAX<kill>, 64, %EFLAGS<imp-def>
%ESI<def,tied1> = CMOVB32rr %ESI<kill,tied0>, %EBP<kill>, %EFLAGS<imp-use>
%ESI<def,tied1> = AND32ri %ESI<kill,tied0>, 4194303, %EFLAGS<imp-def,dead>
%ESI<def,tied1> = XOR32ri8 %ESI<kill,tied0>, 1, %EFLAGS<imp-def,dead>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EDI<def> = COPY %ESI
%EDI<def,tied1> = SHL32rCL %EDI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%EAX<def> = MOV32ri 48
TEST8ri %AL, 32, %EFLAGS<imp-def>, %EAX<imp-use,kill>
%ECX<def> = COPY %EDI
%EAX<def> = MOV32ri 0
%ECX<def,tied1> = CMOVNE32rr %ECX<kill,tied0>, %EAX<kill>, %EFLAGS<imp-use>
%EBP<def> = COPY %ECX<kill>
%ECX<def,dead> = MOV32ri 48, %CL<imp-def>
%EAX<def> = COPY %EDX<kill>
%EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
%EDX<def,tied1> = SHLD32rrCL %EDX<kill,tied0>, %ESI, %EFLAGS<imp-def,dead>,
%CL<imp-use>
%ECX<def> = MOV32ri 48
TEST8ri %CL, 32, %EFLAGS<imp-def>, %ECX<imp-use,kill>
%EDX<def,tied1> = CMOVNE32rr %EDX<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
%EDI<def> = COPY %ESI
CMP32mi8 %ESP, 1, %noreg, 24, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack1]
%ECX<def> = MOV32ri 0
%EDX<def,tied1> = CMOVAE32rr %EDX<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%ECX<def> = MOV32ri 0
%EBP<def,tied1> = CMOVAE32rr %EBP<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
MOV32mr %ESP, 1, %noreg, 4, %noreg, %EBP<kill>; mem:ST4[FixedStack6]
%CL<def> = COPY %BL
%EDI<def,tied1> = SHL32rCL %EDI<kill,tied0>, %EFLAGS<imp-def,dead>,
%CL<imp-use>
TEST8ri %BL, 32, %EFLAGS<imp-def>, %EBX<imp-use,kill>
%EBX<def> = MOV32rm %ESP, 1, %noreg, 28, %noreg; mem:LD4[FixedStack0]
%ECX<def> = MOV32ri 0
%EDI<def,tied1> = CMOVNE32rr %EDI<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%CL<def> = MOV8rm %ESP, 1, %noreg, 8, %noreg; mem:LD1[FixedStack5]
%EBP<def> = MOV32ri 0
%ESI<def,tied1> = SHRD32rrCL %ESI<kill,tied0>, %EBP<kill>,
%EFLAGS<imp-def,dead>, %CL<imp-use>
TEST8ri %CL<kill>, 32, %EFLAGS<imp-def>
%ECX<def> = MOV32ri 0
%ESI<def,tied1> = CMOVNE32rr %ESI<kill,tied0>, %ECX<kill>, %EFLAGS<imp-use>
%ESI<def,tied1> = OR32rm %ESI<kill,tied0>, %ESP, 1, %noreg, 12, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack4]
CMP32mi8 %ESP, 1, %noreg, 24, %noreg, 64, %EFLAGS<imp-def>;
mem:LD4[FixedStack1]
%ESI<def,tied1> = CMOVAE32rr %ESI<kill,tied0>, %EDI<kill>, %EFLAGS<imp-use>
%ECX<def> = MOV32ri 65535
%EAX<def,tied1> = AND32rr %EAX<kill,tied0>, %ECX<kill>,
%EFLAGS<imp-def,dead>
%EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %EDX<kill>,
%EFLAGS<imp-def,dead>
%EDX<def> = COPY %EAX<kill>
%EAX<def> = MOV32rm %ESP, 1, %noreg, 16, %noreg; mem:LD4[FixedStack3]
%ECX<def> = MOV32ri 192
%EAX<def,tied1> = AND32rr %EAX<kill,tied0>, %ECX<kill>,
%EFLAGS<imp-def,dead>
%EAX<def,tied1> = OR32rr %EAX<kill,tied0>, %ESI<kill>,
%EFLAGS<imp-def,dead>
%ESI<def> = MOV32rm %ESP, 1, %noreg, 20, %noreg; mem:LD4[FixedStack2]
%ECX<def> = MOV32ri -1
%EBX<def,tied1> = AND32rr %EBX<kill,tied0>, %ECX<kill>,
%EFLAGS<imp-def,dead>
%EBX<def,tied1> = OR32rm %EBX<kill,tied0>, %ESP, 1, %noreg, 4, %noreg,
%EFLAGS<imp-def,dead>; mem:LD4[FixedStack6]
%EAX<def> = MOVZX32rr8 %AL, %EAX<imp-use,kill>
MOV32mr %noreg, 1, %noreg, <ga:@b>, %noreg, %ESI; mem:ST4[getelementptr
inbounds (%struct.anon* @b, i32 0, i32 0)](align=1)(tbaa=<badref>)
%ESI<def,tied1> = DEC32r %ESI<kill,tied0>, %EFLAGS<imp-def,dead>
CMP32ri8 %ESI, -1, %EFLAGS<imp-def>
JNE_4 <BB#10>, %EFLAGS<imp-use>
Successors according to CFG: BB#11(4) BB#10(124)
BB#11: derived from LLVM BB %for.cond.for.end_crit_edge
Live Ins: %EDX %EAX %EBX
Predecessors according to CFG: BB#10 BB#8 BB#7
MOV32mr %noreg, 1, %noreg, <ga:@d>, %noreg, %EBX<kill>; mem:ST4[bitcast
(%struct.S0* @d to i72*)](align=1)
MOV32mr %noreg, 1, %noreg, <ga:@d+4>, %noreg, %EDX<kill>; mem:ST4[bitcast
(%struct.S0* @d to i72*)+4](align=1)
MOV8mr %noreg, 1, %noreg, <ga:@d+8>, %noreg, %AL, %EAX<imp-use,kill>;
mem:ST1[bitcast (%struct.S0* @d to i72*)+8]
%ECX<def> = MOV32rm %ESP, 1, %noreg, 0, %noreg; mem:LD4[FixedStack7]
Successors according to CFG: BB#12
BB#12: derived from LLVM BB %for.end
Live Ins: %ECX
Predecessors according to CFG: BB#0 BB#11
%EAX<def> = MOV32rm %noreg, 1, %noreg, <ga:@c>, %noreg;
mem:LD4[getelementptr inbounds (%struct.S1* @c, i32 0, i32
0)](align=1)(tbaa=<badref>)
Successors according to CFG: BB#14
BB#14: derived from LLVM BB %return
Live Ins: %AH %AL %AX %CH %CL %CX %EAX %ECX
Predecessors according to CFG: BB#12 BB#9
MOV32mr %ECX<kill>, 1, %noreg, 0, %noreg, %EAX<kill>;
mem:ST4[%17](align=1)(tbaa=<badref>)
Successors according to CFG: BB#13
BB#13: derived from LLVM BB %return
Predecessors according to CFG: BB#14
%ESP<def,tied1> = ADD32ri8 %ESP<tied0>, 32, %EFLAGS<imp-def,dead>
%ESI<def> = POP32r %ESP<imp-def>, %ESP<imp-use>
%EDI<def> = POP32r %ESP<imp-def>, %ESP<imp-use>
%EBX<def> = POP32r %ESP<imp-def>, %ESP<imp-use>
%EBP<def> = POP32r %ESP<imp-def>, %ESP<imp-use>
RETL
# End machine code for function fn1.
*** Bad machine code: Using an undefined physical register ***
- function: fn1
- basic block: BB#9 if.then (0x5265a30)
- instruction: TEST8ri %CH<kill>, 32, %EFLAGS<imp-def>
- operand 0: %CH<kill>
fatal error: error in backend: Found 1 machine code errors.
clang: error: clang frontend command failed with exit code 70 (use -v to see
invocation)
clang version 3.5 (trunk 201500)
Target: i386-unknown-linux-gnu
Thread model: posix
clang: note: diagnostic msg: PLEASE submit a bug report to
http://llvm.org/bugs/ and include the crash backtrace, preprocessed source, and
associated run script.
clang: note: diagnostic msg:
********************
PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang: note: diagnostic msg: /tmp/small-0e7214.c
clang: note: diagnostic msg: /tmp/small-0e7214.sh
clang: note: diagnostic msg:
********************
$
-------------------------
int a;
#pragma pack(1)
struct S0
{
int:7;
int:29;
int f5:12;
int f6:22;
} d;
struct S1
{
int f2;
} c, e;
struct
{
int f0;
} b;
static struct S1
fn1 ()
{
int f;
for (; b.f0; b.f0--)
{
struct S0 g;
d.f6 ^= 1;
f = a ? 1 : 1 << a;
g.f5 = f;
if (!g.f5)
return e;
}
return c;
}
void
fn2 ()
{
fn1 ();
fn1 ();
}
int
main ()
{
fn2 ();
return 0;
}
--
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