[LLVMbugs] [Bug 19565] New: [aarch32] Some predicated assembler instructions are not valid in thumb mode

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=19565

            Bug ID: 19565
           Summary: [aarch32] Some predicated assembler instructions are
                    not valid in thumb mode
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: llc
          Assignee: unassignedbugs at nondot.org
          Reporter: ssijaric at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 12444
  --> http://llvm.org/bugs/attachment.cgi?id=12444&action=edit
ll file for reproducing the issue

Running

llc a.ll -march=thumb -mcpu=cortex-a53 -mattr=+thumb2

produces

...
@ BB#0:                                 @ %entry
        subs    r0, r0, r1
        it      mi
        rsbsmi  r0, r0, #0  <=== not valid, should be rsbmi
        bx      lr
.Ltmp0:
...

Running the GNU assembler on a.s results in:

a.s: Assembler messages:
a.s:30: Warning: it blocks containing wide Thumb instructions are deprecated in
ARMv8

This behaviour is due to the changed flow for Aarch32, where it runs
Thumb2SizeReduce before If Conversion due to the partial IT block deprecation.

Incoming into Thumb2SizeReduce, we have:

# *** IR Dump After Post-RA pseudo instruction expansion pass ***:
# Machine code for function func: Post SSA
Function Live Ins: %R0 in %vreg0, %R1 in %vreg1

BB#0: derived from LLVM BB %entry
    Live Ins: %R0 %R1
        %R0<def> = t2SUBrr %R0<kill>, %R1<kill>, pred:14, pred:%noreg,
opt:%CPSR<def>
        t2Bcc <BB#2>, pred:5, pred:%CPSR
    Successors according to CFG: BB#1 BB#2

BB#1: derived from LLVM BB %entry
    Live Ins: %R0
    Predecessors according to CFG: BB#0
        %R0<def> = t2RSBri %R0<kill>, 0, pred:14, pred:%noreg, opt:%noreg
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %entry
    Live Ins: %R0
    Predecessors according to CFG: BB#1 BB#0
        tBX_RET pred:14, pred:%noreg, %R0<imp-use>



And Thumb2SizeReduce will result in:

Converted 32-bit: %R0<def> = t2RSBri %R0<kill>, 0, pred:14, pred:%noreg,
opt:%noreg
       to 16-bit: %R0<def>, %CPSR<def,dead> = tRSB %R0<kill>, pred:14,
pred:%noreg

Since the t2RSBri is not predicated, the corresponding 16-bit instruction must
set the CPSR, and is marked as such.  If Conversion produces

# *** IR Dump After If Converter ***:
# Machine code for function func: Post SSA
Function Live Ins: %R0 in %vreg0, %R1 in %vreg1

BB#0: derived from LLVM BB %entry
    Live Ins: %R0 %R1
        %R0<def>, %CPSR<def> = tSUBrr %R0<kill>, %R1<kill>, pred:14,
pred:%noreg
        %R0<def>, %CPSR<def,dead> = tRSB %R0<kill>, pred:4, pred:%CPSR,
%R0<imp-use,undef>, %CPSR<imp-use,undef>
        tBX_RET pred:14, pred:%noreg, %R0<imp-use>

# End machine code for function func.

So, tRSB is predicated and sets the CPSR. The logic in isV8EligibleForIT gets
around this by checking if CPSR is dead for a set of instructions that may end
up inside the IT block on ARMv8.  tRSB will end up in the IT block as:

BB#0: derived from LLVM BB %entry
    Live Ins: %R0 %R1
        %R0<def>, %CPSR<def> = tSUBrr %R0<kill>, %R1<kill>, pred:14,
pred:%noreg
        t2IT 4, 8, %ITSTATE<imp-def>
        %R0<def>, %CPSR<def,dead> = tRSB %R0<kill>, pred:4, pred:%CPSR,
%R0<imp-use,undef>, %CPSR<imp-use,undef>, %ITSTATE<imp-use,kill>
        tBX_RET pred:14, pred:%noreg, %R0<imp-use,kill>

# End machine code for function func.

Due to the presence of CPSR, the 's' modifier will be appended to rsb when the
.s file is generated, resulting in rsbsmi.

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