[LLVMbugs] [Bug 19424] New: Port bitfield optimisations from AArch64 to ARM64

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=19424

            Bug ID: 19424
           Summary: Port bitfield optimisations from AArch64 to ARM64
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: t.p.northover at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

ARM64 doesn't currently form enough (any?) BFI instructions, which means it
cannot pass test/CodeGen/bitfield-insert.ll.

AArch64 gets this via a DAG combine (search for "tryCombineToBFI"). However,
there's a wrinkle: transplanting the code directly results in failures in
ARM64's rev.ll test because the early formation of ARM64ISD::BFI nodes
interferes with the normal DAG combines.

However, the AArch64 code relies on (at least) two passes of DAG combine to
reach its optimal form. This is a flaw which means we can't simply disable it
during early combines.

So, the options are:
  + Rewrite it to be recursive and build the final BFI in just one pass.
  + Rewrite it as some C++ ISelDAG code (similarly recursive).

I *suspect* that the second option will give better results, and not be
significantly harder than the first.

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