[LLVMbugs] [Bug 19412] New: Errorneous assumption of 8 bit argument widened to 32 bit
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Sat Apr 12 16:41:55 PDT 2014
http://llvm.org/bugs/show_bug.cgi?id=19412
Bug ID: 19412
Summary: Errorneous assumption of 8 bit argument widened to 32
bit
Product: clang
Version: 3.4
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: LLVM Codegen
Assignee: unassignedclangbugs at nondot.org
Reporter: sebastiangraf at t-online.de
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
When using https://github.com/vmt/udis86, I hit this both on my Mac and my
Linux PC using clang as compiler targeting x64.
To reproduce (python 2.7 is needed as default python, I submitted a pull
request to fix that but it wasn't accepted yet):
1. Download the repository
2. $ ./configure --prefix=`pwd`/bin CC="clang" from the root of the repository
3. $ make && make install (will not make if it couldn't use python 2.7 for
codegen)
4. Examine ud_set_mode in ./bin/lib/libudis.so with gdb
5. $ gdb ./bin/lib/libudis86.so
6. (gdb) info line ud_set_mode
7. (gdb) x/13i 0x11100 (start of ud_set_mode was 0x11100 for me)
This results in the assembly listing for ud_set_mode in ./libudis/udis86.c:86:
(gdb) x/13i 0x11100
0x11100 <ud_set_mode>: lea -0x10(%rsi),%eax
0x11103 <ud_set_mode+3>: cmp $0x30,%eax
0x11106 <ud_set_mode+6>: ja 0x11120 <ud_set_mode+32>
0x11108 <ud_set_mode+8>: movabs $0x1000000010001,%rcx
0x11112 <ud_set_mode+18>: bt %rax,%rcx
0x11116 <ud_set_mode+22>: jae 0x11120 <ud_set_mode+32>
0x11118 <ud_set_mode+24>: mov %sil,0x170(%rdi)
0x1111f <ud_set_mode+31>: retq
0x11120 <ud_set_mode+32>: movb $0x10,0x170(%rdi)
0x11127 <ud_set_mode+39>: retq
0x11128: nopl 0x0(%rax,%rax,1)
0x11130 <ud_set_pc>: mov %rsi,0x178(%rdi)
0x11137 <ud_set_pc+7>: retq
Note that the 8 bit argument m is assumed to be 32 bits wide in 0x11103. For
completeness sake, the assembly output from udis86.s generated by using clang
-S ...:
ud_set_mode: # @ud_set_mode
.cfi_startproc
# BB#0:
# kill: ESI<def> ESI<kill> RSI<def>
leal -16(%rsi), %eax
cmpl $48, %eax
ja .LBB1_3
# BB#1:
movabsq $281474976776193, %rcx # imm = 0x1000000010001
btq %rax, %rcx
jae .LBB1_3
# BB#2:
movb %sil, 368(%rdi)
ret
The respective IR:
Function Attrs: nounwind uwtable
define void @ud_set_mode(%struct.ud* nocapture %u, i8 zeroext %m) #0 {
%1 = zext i8 %m to i32
switch i32 %1, label %4 [
i32 16, label %2
i32 32, label %2
i32 64, label %2
]
; <label>:2 ; preds = %0, %0, %0
%3 = getelementptr inbounds %struct.ud* %u, i64 0, i32 18
store i8 %m, i8* %3, align 1, !tbaa !1
br label %6
; <label>:4 ; preds = %0
%5 = getelementptr inbounds %struct.ud* %u, i64 0, i32 18
store i8 16, i8* %5, align 1, !tbaa !1
br label %6
; <label>:6 ; preds = %4, %2
ret void
}
And the C function:
extern void
ud_set_mode(struct ud* u, uint8_t m)
{
switch(m) {
case 16:
case 32:
case 64: u->dis_mode = m ; return;
default: u->dis_mode = 16; return;
}
}
The IR actually seems to be correct, so maybe this is more of a backend issue.
The zero extension obviously doesn't happen. I wasn't able to reproduce it with
a more simple case, so I'm sorry for that rather long reproduction recipe.
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