[LLVMbugs] [Bug 19362] New: ARM disassembler ignores negative offset bit for ldrht, ldrsht, strht, and ldrsbt

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=19362

            Bug ID: 19362
           Summary: ARM disassembler ignores negative offset bit for
                    ldrht, ldrsht, strht, and ldrsbt
           Product: new-bugs
           Version: 3.4
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: dpmiller at cmu.edu
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Disassembling ldrht, ldrsht, strht, and ldrsbt with llvm-mc produces
instructions without the optional negative sign in front of the optional
offset. All offsets are disassembled as a positive offset, regardless of the
sign bit.

Code to reproduce:
$ echo "ldrht r1, [r2], -r3" | llvm-mc -arch=arm -show-inst
    .text
    ldrht    r1, [r2], -r3           @ <MCInst #217 LDRHTr
                                        @  <MCOperand Reg:67>
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Imm:0>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

Notice that the Imm is 0. Compare with the disassembly for ldrh in which bit 8
of the immediate is properly set:

$ echo "ldrh r1, [r2], -r3" | llvm-mc -arch=arm -show-inst
    .text
    ldrh    r1, [r2], -r3           @ <MCInst #218 LDRH_POST
                                        @  <MCOperand Reg:67>
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Imm:256>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

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