[LLVMbugs] [Bug 17408] New: constant propagation for SSE intrinsics

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Sun Sep 29 23:27:50 PDT 2013


http://llvm.org/bugs/show_bug.cgi?id=17408

            Bug ID: 17408
           Summary: constant propagation for SSE intrinsics
           Product: clang
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Headers
          Assignee: unassignedclangbugs at nondot.org
          Reporter: kretz at kde.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 11301
  --> http://llvm.org/bugs/attachment.cgi?id=11301&action=edit
patch  to emmintrin.h

Hi,

I was looking into constant propagation for this simple testcase:
#include <xmmintrin.h>
__m128 cvt() { return _mm_cvtepi32_ps(_mm_set1_epi32(2)); }

clang turns this into a cvtdq2ps instruction even though it could just store a
float-vector constant and load it without conversion.

Chandler pointed me to the possiblity of solving this in emmintrin.h with the
following patch:
@@ -1011,7 +1011,8 @@
 static __inline__ __m128 __attribute__((__always_inline__, __nodebug__))
 _mm_cvtepi32_ps(__m128i __a)
 {
-  return __builtin_ia32_cvtdq2ps((__v4si)__a);
+  __v4si __b = (__v4si)__a;
+  return (__m128)(__v4sf) { __b[0], __b[1], __b[2], __b[3] };
 }

Now the cvt function is translated to a single movaps from a float-vector
constant. The testcase:
__m128 cvt(__m128i x) { return _mm_cvtepi32_ps(x); }
still compiles, as expected, to a cvtdq2ps instruction. But the IR is very
verbose now (before it was an explicit call to x86.sse2.cvtdq2ps):
define <4 x float> @_Z3cvtDv2_x(<2 x i64> %x) #0 {
  %1 = bitcast <2 x i64> %x to <4 x i32>
  %2 = extractelement <4 x i32> %1, i32 0
  %3 = sitofp i32 %2 to float
  %4 = insertelement <4 x float> undef, float %3, i32 0
  %5 = extractelement <4 x i32> %1, i32 1
  %6 = sitofp i32 %5 to float
  %7 = insertelement <4 x float> %4, float %6, i32 1
  %8 = extractelement <4 x i32> %1, i32 2
  %9 = sitofp i32 %8 to float
  %10 = insertelement <4 x float> %7, float %9, i32 2
  %11 = extractelement <4 x i32> %1, i32 3
  %12 = sitofp i32 %11 to float
  %13 = insertelement <4 x float> %10, float %12, i32 3
  ret <4 x float> %13
}

Is this kind of patches to the SIMD intrinsics interesting? Then I'd work on
looking for more issues of this kind.

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