[LLVMbugs] [Bug 18007] New: X86 backend epic fail at generating decent code for some obvious bit math
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Wed Nov 20 11:43:09 PST 2013
http://llvm.org/bugs/show_bug.cgi?id=18007
Bug ID: 18007
Summary: X86 backend epic fail at generating decent code for
some obvious bit math
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: unassignedbugs at nondot.org
Reporter: chandlerc at gmail.com
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
This is kinda sad.
% cat x.cpp
unsigned g(unsigned i, bool b1, bool b2, bool b3) {
unsigned cookie_mask = ~(7 << 29);
return ((i & cookie_mask) | (b1 << 31) | (b2 << 30) | (b3 << 29));
}
% ./bin/clang++ -O2 -S -emit-llvm -o - x.cpp
; ModuleID = 'x.c'
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind readnone uwtable
define i32 @_Z1gjbbb(i32 %i, i1 zeroext %b1, i1 zeroext %b2, i1 zeroext %b3) #0
{
entry:
%and = and i32 %i, 536870911
%conv = zext i1 %b1 to i32
%shl = shl nuw i32 %conv, 31
%or = or i32 %shl, %and
%conv4 = zext i1 %b2 to i32
%shl5 = shl nuw nsw i32 %conv4, 30
%or6 = or i32 %or, %shl5
%conv8 = zext i1 %b3 to i32
%shl9 = shl nuw nsw i32 %conv8, 29
%or10 = or i32 %or6, %shl9
ret i32 %or10
}
attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false"
"no-frame-pointer-elim"="false" "no-infs-fp-math"="false"
"no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
"unsafe-fp-math"="false" "use-soft-float"="false" }
!llvm.ident = !{!0}
!0 = metadata !{metadata !"clang version 3.4 "}
Totally reasonable. Exactly what I would expect. nuw and nsw all over the
place, nothing ambiguous, etc.
% ./bin/clang++ -O2 -S -o - x.cpp
.file "x.cpp"
.text
.globl _Z1gjbbb
.align 16, 0x90
.type _Z1gjbbb, at function
_Z1gjbbb: # @_Z1gjbbb
.cfi_startproc
# BB#0: # %entry
andl $536870911, %edi # imm = 0x1FFFFFFF
movzbl %sil, %eax
shll $31, %eax
orl %edi, %eax
movzbl %dl, %edx
shll $30, %edx
orl %eax, %edx
movzbl %cl, %eax
shll $29, %eax
orl %edx, %eax
ret
.Ltmp1:
.size _Z1gjbbb, .Ltmp1-_Z1gjbbb
.cfi_endproc
What on earth is this???
movzbl? We're about to shift out the high bits. Copying between registers? WAT
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