[LLVMbugs] [Bug 17865] New: Assertion `(I.atEnd() || llvm::next(I) == def_end()) && "getVRegDef assumes a single definition or no definition"' failed.

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Sat Nov 9 12:47:13 PST 2013


http://llvm.org/bugs/show_bug.cgi?id=17865

            Bug ID: 17865
           Summary: Assertion `(I.atEnd() || llvm::next(I) == def_end())
                    && "getVRegDef assumes a single definition or no
                    definition"' failed.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PTX
          Assignee: unassignedbugs at nondot.org
          Reporter: maemarcus at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

As of r192445 NVPTX backend crashes on a reduced test case (note this is really
a bugpoint-reduced test case, although it's large!):

$ kernelgen-llc -version
LLVM (http://llvm.org/):
  LLVM version 3.4svn
  DEBUG build with assertions.
  Built Nov  3 2013 (05:21:36).
  Default target: x86_64-unknown-linux-gnu
  Host CPU: core-avx-i

  Registered Targets:
    nvptx   - NVIDIA PTX 32-bit
    nvptx64 - NVIDIA PTX 64-bit
    x86     - 32-bit X86: Pentium-Pro and above
    x86-64  - 64-bit X86: EM64T and AMD64

$ cat badri_crash.ll
; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
target triple = "nvptx64-nvidia-cuda"

@memoryForKernelArgs = external global [2448 x i8], align 4096
@replacementOfAlloca368 = external global [3 x i32], align 4096

; Function Attrs: nounwind uwtable
define ptx_device void @m_kf_analog() #0 {
entry:
  br i1 undef, label %"17", label %"15_orig"

"15_orig":                                        ; preds = %entry
  unreachable

"17":                                             ; preds = %entry
  br i1 undef, label %"20", label %"18_orig"

"18_orig":                                        ; preds = %"17"
  unreachable

"20":                                             ; preds = %"17"
  br i1 undef, label %"25_orig.header", label %"26"

"24_orig":                                        ; preds = %"25_orig.header"
  br label %"25_orig.header"

"25_orig.header":                                 ; preds = %"24_orig", %"20"
  br i1 undef, label %"26", label %"24_orig"

"26":                                             ; preds = %"25_orig.header",
%"20"
  br i1 undef, label %"770_orig.header", label %"771"

"28_orig_orig":                                   ; preds =
%"768_orig_orig.header"
  %or.cond13 = or i1 undef, undef
  br i1 %or.cond13, label %"31_orig_orig", label %"29_orig_orig_orig"

"29_orig_orig_orig":                              ; preds = %"28_orig_orig"
  unreachable

"31_orig_orig":                                   ; preds = %"28_orig_orig"
  br i1 undef, label %"32_orig_orig", label %"766_orig_orig"

"32_orig_orig":                                   ; preds = %"31_orig_orig"
  br i1 undef, label %"34_orig_orig", label %"33_orig_orig"

"33_orig_orig":                                   ; preds = %"32_orig_orig"
  br i1 undef, label %"34_orig_orig", label %"35_orig_orig"

"34_orig_orig":                                   ; preds = %"33_orig_orig",
%"32_orig_orig"
  %or.cond3 = or i1 undef, undef
  br i1 %or.cond3, label %"47_orig_orig", label %"39_orig_orig_orig"

"35_orig_orig":                                   ; preds = %"33_orig_orig"
  unreachable

"39_orig_orig_orig":                              ; preds = %"34_orig_orig"
  unreachable

"47_orig_orig":                                   ; preds = %"34_orig_orig"
  br i1 undef, label %"61_orig_orig", label %"60_orig_orig"

"60_orig_orig":                                   ; preds = %"47_orig_orig"
  br label %"61_orig_orig"

"61_orig_orig":                                   ; preds = %"60_orig_orig",
%"47_orig_orig"
  br i1 undef, label %"69_orig_orig_orig.header", label %"70_orig_orig"

"68_orig_orig_orig":                              ; preds =
%"69_orig_orig_orig.header"
  br label %"69_orig_orig_orig.header"

"69_orig_orig_orig.header":                       ; preds =
%"68_orig_orig_orig", %"61_orig_orig"
  br i1 undef, label %"70_orig_orig", label %"68_orig_orig_orig"

"70_orig_orig":                                   ; preds =
%"69_orig_orig_orig.header", %"61_orig_orig"
  %or.cond = or i1 undef, undef
  br i1 %or.cond, label %"106_orig_orig", label %"98_orig_orig_orig"

"98_orig_orig_orig":                              ; preds = %"70_orig_orig"
  unreachable

"106_orig_orig":                                  ; preds = %"70_orig_orig"
  %or.cond8 = or i1 undef, undef
  br i1 %or.cond8, label %"112_orig_orig", label %"107_orig_orig_orig"

"107_orig_orig_orig":                             ; preds = %"106_orig_orig"
  unreachable

"112_orig_orig":                                  ; preds = %"106_orig_orig"
  %or.cond10 = or i1 undef, undef
  br i1 %or.cond10, label %"151_orig_orig", label %"146_orig_orig_orig"

"146_orig_orig_orig":                             ; preds = %"112_orig_orig"
  unreachable

"151_orig_orig":                                  ; preds = %"112_orig_orig"
  %or.cond1 = or i1 undef, undef
  br i1 %or.cond1, label %"172_orig_orig", label %"164_orig_orig_orig"

"164_orig_orig_orig":                             ; preds = %"151_orig_orig"
  unreachable

"172_orig_orig":                                  ; preds = %"151_orig_orig"
  br i1 undef, label %"192_orig_orig_orig.header", label %"193_orig_orig"

"191_orig_orig_orig":                             ; preds =
%"192_orig_orig_orig.header"
  br label %"192_orig_orig_orig.header"

"192_orig_orig_orig.header":                      ; preds =
%"191_orig_orig_orig", %"172_orig_orig"
  br i1 undef, label %"193_orig_orig", label %"191_orig_orig_orig"

"193_orig_orig":                                  ; preds =
%"192_orig_orig_orig.header", %"172_orig_orig"
  %or.cond9 = or i1 undef, undef
  br i1 %or.cond9, label %"205_orig_orig", label %"197_orig_orig_orig"

"197_orig_orig_orig":                             ; preds = %"193_orig_orig"
  unreachable

"205_orig_orig":                                  ; preds = %"193_orig_orig"
  %or.cond4 = or i1 undef, undef
  br i1 %or.cond4, label %"246_orig_orig", label
%"243.preheader_orig_orig_orig"

"243.preheader_orig_orig_orig":                   ; preds = %"205_orig_orig"
  unreachable

"246_orig_orig":                                  ; preds = %"205_orig_orig"
  br i1 undef, label %"287_orig_orig_orig.header", label %"288_orig_orig"

"286_orig_orig_orig":                             ; preds =
%"287_orig_orig_orig.header"
  br label %"287_orig_orig_orig.header"

"287_orig_orig_orig.header":                      ; preds =
%"286_orig_orig_orig", %"246_orig_orig"
  br i1 undef, label %"288_orig_orig", label %"286_orig_orig_orig"

"288_orig_orig":                                  ; preds =
%"287_orig_orig_orig.header", %"246_orig_orig"
  %or.cond14 = or i1 undef, undef
  br i1 %or.cond14, label %"306_orig_orig", label %"298_orig_orig_orig"

"298_orig_orig_orig":                             ; preds = %"288_orig_orig"
  unreachable

"306_orig_orig":                                  ; preds = %"288_orig_orig"
  %or.cond2 = or i1 undef, undef
  br i1 %or.cond2, label %"318_orig_orig", label %"313_orig_orig_orig"

"313_orig_orig_orig":                             ; preds = %"306_orig_orig"
  unreachable

"318_orig_orig":                                  ; preds = %"306_orig_orig"
  %or.cond5 = or i1 undef, undef
  br i1 %or.cond5, label %"333_orig_orig", label %"325_orig_orig_orig"

"325_orig_orig_orig":                             ; preds = %"318_orig_orig"
  unreachable

"333_orig_orig":                                  ; preds = %"318_orig_orig"
  %or.cond16 = or i1 undef, undef
  br i1 %or.cond16, label %"345_orig_orig", label
%"342.preheader_orig_orig_orig"

"342.preheader_orig_orig_orig":                   ; preds = %"333_orig_orig"
  unreachable

"345_orig_orig":                                  ; preds = %"333_orig_orig"
  %or.cond11 = or i1 undef, undef
  br i1 %or.cond11, label %"372_orig_orig", label %"367_orig_orig_orig"

"367_orig_orig_orig":                             ; preds = %"345_orig_orig"
  unreachable

"372_orig_orig":                                  ; preds = %"345_orig_orig"
  br i1 undef, label %"383_orig_orig_orig.header", label %"384_orig_orig"

"382_orig_orig_orig":                             ; preds =
%"383_orig_orig_orig.header"
  br label %"383_orig_orig_orig.header"

"383_orig_orig_orig.header":                      ; preds =
%"382_orig_orig_orig", %"372_orig_orig"
  br i1 undef, label %"384_orig_orig", label %"382_orig_orig_orig"

"384_orig_orig":                                  ; preds =
%"383_orig_orig_orig.header", %"372_orig_orig"
  br i1 false, label %"385_orig_orig", label %"448_orig_orig"

"385_orig_orig":                                  ; preds = %"384_orig_orig"
  unreachable

"448_orig_orig":                                  ; preds = %"384_orig_orig"
  %0 = fcmp une double undef, 0.000000e+00
  br i1 %0, label %"450_orig_orig", label %"490_orig_orig"

"450_orig_orig":                                  ; preds = %"448_orig_orig"
  br i1 undef, label %"455_orig_orig_orig.header", label %"456_orig_orig"

"454_orig_orig_orig":                             ; preds =
%"455_orig_orig_orig.header"
  br label %"455_orig_orig_orig.header"

"455_orig_orig_orig.header":                      ; preds =
%"454_orig_orig_orig", %"450_orig_orig"
  br i1 undef, label %"456_orig_orig", label %"454_orig_orig_orig"

"456_orig_orig":                                  ; preds =
%"455_orig_orig_orig.header", %"450_orig_orig"
  br i1 undef, label %"475_orig_orig", label %"478_orig_orig"

"475_orig_orig":                                  ; preds = %"456_orig_orig"
  br label %"478_orig_orig"

"478_orig_orig":                                  ; preds = %"475_orig_orig",
%"456_orig_orig"
  br i1 undef, label %"481_orig_orig", label %"480_orig_orig"

"480_orig_orig":                                  ; preds = %"478_orig_orig"
  br label %"481_orig_orig"

"481_orig_orig":                                  ; preds = %"480_orig_orig",
%"478_orig_orig"
  br i1 undef, label %"489_orig_orig_orig.header", label %"565_orig_orig"

"488_orig_orig_orig":                             ; preds =
%"489_orig_orig_orig.header"
  br label %"489_orig_orig_orig.header"

"489_orig_orig_orig.header":                      ; preds =
%"488_orig_orig_orig", %"481_orig_orig"
  br i1 undef, label %"565_orig_orig", label %"488_orig_orig_orig"

"490_orig_orig":                                  ; preds = %"448_orig_orig"
  unreachable

"565_orig_orig":                                  ; preds =
%"489_orig_orig_orig.header", %"481_orig_orig"
  %or.cond7 = or i1 undef, undef
  br i1 %or.cond7, label %"626_orig_orig", label %"624_orig_orig_orig"

"624_orig_orig_orig":                             ; preds = %"565_orig_orig"
  unreachable

"626_orig_orig":                                  ; preds = %"565_orig_orig"
  br i1 undef, label %"764_orig_orig", label %"630_orig_orig"

"630_orig_orig":                                  ; preds = %"626_orig_orig"
  br i1 false, label %"631_orig_orig", label %"722_orig_orig"

"631_orig_orig":                                  ; preds = %"630_orig_orig"
  unreachable

"722_orig_orig":                                  ; preds = %"630_orig_orig"
  %or.cond6 = or i1 undef, undef
  br i1 %or.cond6, label %"743_orig_orig", label %"732_orig_orig_orig"

"732_orig_orig_orig":                             ; preds = %"722_orig_orig"
  unreachable

"743_orig_orig":                                  ; preds = %"722_orig_orig"
  %or.cond12 = or i1 undef, undef
  br i1 %or.cond12, label %"752_orig_orig", label %"750_orig_orig_orig"

"750_orig_orig_orig":                             ; preds = %"743_orig_orig"
  unreachable

"752_orig_orig":                                  ; preds = %"743_orig_orig"
  %or.cond15 = or i1 undef, undef
  br i1 %or.cond15, label %"767_orig_orig", label %"753_orig_orig_orig"

"753_orig_orig_orig":                             ; preds = %"752_orig_orig"
  unreachable

"764_orig_orig":                                  ; preds = %"626_orig_orig"
  store double 0.000000e+00, double* undef, align 8
  br label %"767_orig_orig"

"766_orig_orig":                                  ; preds = %"31_orig_orig"
  store i32 undef, i32* getelementptr inbounds ([3 x i32]*
@replacementOfAlloca368, i64 0, i64 2), align 4
  br label %"767_orig_orig"

"767_orig_orig":                                  ; preds = %"766_orig_orig",
%"764_orig_orig", %"752_orig_orig"
  %1 = add i32 %2, 1
  br label %"768_orig_orig.header"

loadOutputsAndSwitchExit1707:                     ; preds =
%"768.preheader_orig"
  %.reload = load i8* getelementptr inbounds ([2448 x i8]*
@memoryForKernelArgs, i64 0, i64 2440), align 8
  br label %"769_orig"

"768_orig_orig.header":                           ; preds =
%"768.preheader_orig", %"767_orig_orig"
  %2 = phi i32 [ %1, %"767_orig_orig" ], [ 1, %"768.preheader_orig" ]
  %3 = icmp ult i32 undef, %2
  br i1 %3, label %"769_orig", label %"28_orig_orig"

"769_orig":                                       ; preds =
%"768_orig_orig.header", %loadOutputsAndSwitchExit1707
  %newPHINode = phi i8 [ %.reload, %loadOutputsAndSwitchExit1707 ], [ undef,
%"768_orig_orig.header" ]
  br label %"770_orig.header"

"770_orig.header":                                ; preds = %"769_orig", %"26"
  %4 = phi i8 [ %newPHINode, %"769_orig" ], [ undef, %"26" ]
  br i1 false, label %"771", label %"768.preheader_orig"

"768.preheader_orig":                             ; preds = %"770_orig.header"
  store i8 %4, i8* getelementptr inbounds ([2448 x i8]* @memoryForKernelArgs,
i64 0, i64 16), align 16
  br i1 undef, label %"768_orig_orig.header", label
%loadOutputsAndSwitchExit1707

"771":                                            ; preds = %"770_orig.header",
%"26"
  ret void
}

attributes #0 = { nounwind uwtable "no-frame-pointer-elim-non-leaf"="true" }

!nvvm.annotations = !{!956}

!956 = metadata !{null, metadata !"kernel", i32 1}

$ kernelgen-llc badri_crash.ll
kernelgen-llc:
/media/scratch/r2218_llvm192445_debug/BUILD/llvm/lib/CodeGen/MachineRegisterInfo.cpp:309:
llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const:
Assertion `(I.atEnd() || llvm::next(I) == def_end()) && "getVRegDef assumes a
single definition or no definition"' failed.
0  libLLVM-3.4svn.so 0x00007fdef5e27081 llvm::sys::PrintStackTrace(_IO_FILE*) +
38
1  libLLVM-3.4svn.so 0x00007fdef5e272fe
2  libLLVM-3.4svn.so 0x00007fdef5e26d5d
3  libpthread.so.0   0x00007fdef471ecb0
4  libc.so.6         0x00007fdef3a57425 gsignal + 53
5  libc.so.6         0x00007fdef3a5ab8b abort + 379
6  libc.so.6         0x00007fdef3a500ee
7  libc.so.6         0x00007fdef3a50192
8  libLLVM-3.4svn.so 0x00007fdef55eb3fe
llvm::MachineRegisterInfo::getVRegDef(unsigned int) const + 202
9  libLLVM-3.4svn.so 0x00007fdef56de64e
10 libLLVM-3.4svn.so 0x00007fdef56deba5
11 libLLVM-3.4svn.so 0x00007fdef56ddef6
12 libLLVM-3.4svn.so 0x00007fdef55b9685
llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
13 libLLVM-3.4svn.so 0x00007fdef5827d5e
llvm::FPPassManager::runOnFunction(llvm::Function&) + 290
14 libLLVM-3.4svn.so 0x00007fdef5827ece
llvm::FPPassManager::runOnModule(llvm::Module&) + 84
15 libLLVM-3.4svn.so 0x00007fdef5828222
llvm::MPPassManager::runOnModule(llvm::Module&) + 556
16 libLLVM-3.4svn.so 0x00007fdef5828818
llvm::PassManagerImpl::run(llvm::Module&) + 244
17 libLLVM-3.4svn.so 0x00007fdef5828a23 llvm::PassManager::run(llvm::Module&) +
39
18 kernelgen-llc     0x000000000040ee48
19 kernelgen-llc     0x000000000040df27 main + 237
20 libc.so.6         0x00007fdef3a4276d __libc_start_main + 237
21 kernelgen-llc     0x000000000040d849
Stack dump:
0.    Program arguments: kernelgen-llc badri_crash.ll 
1.    Running pass 'Function Pass Manager' on module 'badri_crash.ll'.
2.    Running pass 'Tail Duplication' on function '@m_kf_analog'
Aborted (core dumped)

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