[LLVMbugs] [Bug 15603] New: SROA fix for PR14972 introduced a new regression

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=15603

            Bug ID: 15603
           Summary: SROA fix for PR14972 introduced a new regression
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: bob.wilson at apple.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Chandler's fix in svn r177055 for PR14972 seems to have introduced or exposed a
new problem. Here's a non-executable testcase:

$ cat test.ii
bool OSAtomicCompareAndSwap32Barrier(int, int, volatile int *);

class Synchronizer {
public:
 void Swap();

private:
 union DoubleAtomicCASValue {
  struct TheTwoSwapFlags {
   volatile short flag1;
   volatile short flag2;
  } s;
  volatile int flags;
 };

 DoubleAtomicCASValue value;
};

inline
void Synchronizer::Swap()
{
 DoubleAtomicCASValue CompVal;
 DoubleAtomicCASValue StoreVal;

 CompVal.s.flag2 = !value.s.flag1;
 CompVal.s.flag1 = value.s.flag1;

 StoreVal.s.flag2 = !value.s.flag1;
 StoreVal.s.flag1 = !value.s.flag1;

 OSAtomicCompareAndSwap32Barrier(CompVal.flags, StoreVal.flags, &value.flags);
}

void test(Synchronizer *mSynchronizer) {
 mSynchronizer->Swap();
}

$ ~/local/llvm/install/bin/clang -arch armv7 -Os -S test.ii

$ grep strh test.s
    strh.w    r1, [sp, #6]
    strh.w    r1, [sp, #2]
$ # bug: there should be 4 strh instructions

Instead of the 4 16-bit stores, current trunk is using 32-bit stores to [sp,
#4] and [sp], clobbering the values stored by the strh instructions.  Here's
the full code that I'm getting right now:


__Z4testP12Synchronizer:
@ BB#0:                                 @ %entry
        push    {r7, lr}
        mov     r7, sp
        sub     sp, #8
        mov     r2, r0
        movs    r0, #0
        ldrh    r1, [r2]
        cmp     r1, #0
        mov.w   r1, #0
        it      eq
        moveq   r1, #1
        strh.w  r1, [sp, #6]
        ldrh    r1, [r2]
        str     r1, [sp, #4] # BUG: This should be a strh
        ldrh    r1, [r2]
        cmp     r1, #0
        mov.w   r1, #0
        it      eq
        moveq   r1, #1
        strh.w  r1, [sp, #2]
        ldrh    r1, [r2]
        cmp     r1, #0
        it      eq
        moveq   r0, #1
        str     r0, [sp] # BUG: This should be a strh
        ldr     r0, [sp, #4]
        ldr     r1, [sp]
        blx     __Z31OSAtomicCompareAndSwap32BarrieriiPVi
        add     sp, #8
        pop     {r7, pc}

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