[LLVMbugs] [Bug 16640] New: FastISel doesn't respect vector alignment requirements

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=16640

            Bug ID: 16640
           Summary: FastISel doesn't respect vector alignment requirements
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: boulos at cs.stanford.edu
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 10885
  --> http://llvm.org/bugs/attachment.cgi?id=10885&action=edit
Input source

I ran across some code in a project that seems to be a bug in FastISel
triggered by the new vectorizer in LLVM 3.3 (which doesn't seem to have a bug
version available yet in bugzilla).  I have a loop like this:

  int* x;

  for (i = 0; i < len; i++) {
    x[i] = i;
  }

which the new vectorizer dutifully vectorizes.  If I run with FastISel and x
doesn't end up 16-byte aligned, however, I get a segfault (seemingly
incorrectly, this is really just an unaligned access with SSE).  The fault is
caused by LLVM generating movdqa instead of movdqu.  The body of the vectorized
IR has stores like so:

  store <4 x i32> %induction18.i, <4 x i32>* %5, align 4

so the vectorizer and other bits itself seem to be just fine, but FastISel is
probably choosing the wrong vector store instruction.  I couldn't track down
where in the FastISel codepath this happens, but hopefully someone more
familiar with it will see it.

Original simplified source and bitcode attached.  To repro:

  clang -emit-llvm -c -O3 bad-vec.c -o bad-vec.bc
  llvm-dis bad-vec.bc # for inspection
  lli -O3 -fast-isel bad-vec.ll abcdefghi 4

The first argument generates the length of the array, while the second argument
is a dynamic offset (the optimization passes are too clever for me to embed
this in the source).

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