[LLVMbugs] [Bug 15259] New: CodeGen/AArch64/bitfield-insert.ll fails on Builder llvm-mips-linux

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=15259

            Bug ID: 15259
           Summary: CodeGen/AArch64/bitfield-insert.ll fails on Builder
                    llvm-mips-linux
           Product: libraries
           Version: trunk
          Hardware: Other
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: dgilmore at mips.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

The MIPS build bot went red at:

http://lab.llvm.org:8011/builders/llvm-mips-linux/builds/978

There is nothing wrong with the associated commit r175006. The build bot
configuration changed at that point (previously LLVM was configured debug,
at 978 the configuration was changed to release since the memory requirements
for debug builds was causing a good number of build failures).

The debug build generates:

The release build of LLVM generates:

# *** IR Dump After Expand ISel Pseudo-instructions ***:
# Machine code for function from_clang: SSA
Function Live Ins: %X0 in %vreg0, %X1 in %vreg1

BB#0: derived from LLVM BB %entry
    Live Ins: %X0 %X1
    %vreg1<def> = COPY %X1; GPR64:%vreg1
    %vreg0<def> = COPY %X0; GPR64:%vreg0
    %vreg2<def> = COPY %vreg1:sub_32; GPR32:%vreg2 GPR64:%vreg1
    %vreg4<def> = IMPLICIT_DEF; GPR64:%vreg4
    %vreg3<def,tied1> = INSERT_SUBREG %vreg4<tied0>, %vreg2<kill>, sub_32;
GPR64:%vreg3,%vreg4 GPR32:%vreg2
    %vreg5<def,tied1> = BFIxxii %vreg0<tied0>, %vreg3<kill>, 61, 3;
GPR64:%vreg5,%vreg0,%vreg3
    %X0<def> = COPY %vreg5; GPR64:%vreg5
    RET %X0<imp-use>

The build bot is running on a 32-bit big endian machine, which may explain why
the issue is not being seen on other build-bots.




To due memory limitations on the build bot we change changed the configuration
for the build of LLVM from debug to release.

The debug build generates:

# *** IR Dump After Expand ISel Pseudo-instructions ***:
# Machine code for function from_clang: SSA
Function Live Ins: %X0 in %vreg0, %X1 in %vreg1


BB#0: derived from LLVM BB %entry
    Live Ins: %X0 %X1
    %vreg1<def> = COPY %X1; GPR64:%vreg1
    %vreg0<def> = COPY %X0; GPR64:%vreg0
    %vreg2<def> = COPY %vreg1:sub_32; GPR32:%vreg2 GPR64:%vreg1
    %vreg4<def> = IMPLICIT_DEF; GPR64:%vreg4
    %vreg3<def,tied1> = INSERT_SUBREG %vreg4<tied0>, %vreg2<kill>, sub_32;
GPR64:%vreg3,%vreg4 GPR32:%vreg2
    %vreg5<def> = COPY %vreg3:sub_32; GPR32:%vreg5 GPR64:%vreg3
    %vreg6<def> = COPY %vreg0:sub_32; GPR32:%vreg6 GPR64:%vreg0
    %vreg7<def,tied1> = BFIwwii %vreg6<tied0>, %vreg5<kill>, 29, 3;
GPR32:%vreg7,%vreg6,%vreg5
    %vreg8<def> = SUBREG_TO_REG 0, %vreg7<kill>, 3; GPR64:%vreg8 GPR32:%vreg7
    %X0<def> = COPY %vreg8; GPR64:%vreg8
    RET %X0<imp-use>

The release build of LLVM generates:

# *** IR Dump After Expand ISel Pseudo-instructions ***:
# Machine code for function from_clang: SSA
Function Live Ins: %X0 in %vreg0, %X1 in %vreg1

BB#0: derived from LLVM BB %entry
    Live Ins: %X0 %X1
    %vreg1<def> = COPY %X1; GPR64:%vreg1
    %vreg0<def> = COPY %X0; GPR64:%vreg0
    %vreg2<def> = COPY %vreg1:sub_32; GPR32:%vreg2 GPR64:%vreg1
    %vreg4<def> = IMPLICIT_DEF; GPR64:%vreg4
    %vreg3<def,tied1> = INSERT_SUBREG %vreg4<tied0>, %vreg2<kill>, sub_32;
GPR64:%vreg3,%vreg4 GPR32:%vreg2
    %vreg5<def,tied1> = BFIxxii %vreg0<tied0>, %vreg3<kill>, 61, 3;
GPR64:%vreg5,%vreg0,%vreg3
    %X0<def> = COPY %vreg5; GPR64:%vreg5
    RET %X0<imp-use>

We are currently investigating the failure.

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