[LLVMbugs] [Bug 16830] New: MS inline asm conflicts with base pointer register

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Wed Aug 7 15:39:23 PDT 2013


http://llvm.org/bugs/show_bug.cgi?id=16830

            Bug ID: 16830
           Summary: MS inline asm conflicts with base pointer register
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: rnk at google.com
                CC: llvmbugs at cs.uiuc.edu
            Blocks: 13340
    Classification: Unclassified

So far as I can tell, the only register you can't touch in MS inline asm is
ebp, but LLVM's x86 backend requires a BasePtr register which is separate from
the frame pointer in ebp.  It happens to hard code the choice of esi in
X86RegisterInfo.cpp:
  // Use a callee-saved register as the base pointer.  These registers must
  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
  // requires GOT in the EBX register before function calls via PLT GOT
pointer.
  BasePtr = Is64Bit ? X86::RBX : X86::ESI;

This will blow up if the inline asm clobbers esi.

Test case straight from LLVM's own lib/Support/Host.cpp:

bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
                        unsigned *rECX, unsigned *rEDX) {
  __asm {
    mov   eax,value
    cpuid
    mov   esi,rEAX
    mov   dword ptr [esi],eax
    mov   esi,rEBX
    mov   dword ptr [esi],ebx
    mov   esi,rECX
    mov   dword ptr [esi],ecx
    mov   esi,rEDX
    mov   dword ptr [esi],edx
  }
  return false;
}

This generates x86 asm like:

$ clang -cc1 -fms-compatibility t.cpp -o - -cxx-abi microsoft -S
...
"?GetX86CpuIDAndInfo@@YA_NIPAI000 at Z":
        pushl   %ebp
        movl    %esp, %ebp
        pushl   %ebx
        pushl   %edi
        pushl   %esi
        subl    $28, %esp
        movl    %esp, %esi
...
        #APP
        .intel_syntax
        mov eax,dword ptr [esi + 24]
        cpuid
        mov esi,dword ptr [esi + 20]
        mov dword ptr [esi],eax
        mov esi,dword ptr [esi + 16]
        mov dword ptr [esi],ebx
        mov esi,dword ptr [esi + 12]
        mov dword ptr [esi],ecx
        mov esi,dword ptr [esi + 8]
        mov dword ptr [esi],edx
        .att_syntax
        #NO_APP

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