[LLVMbugs] [Bug 13954] New: [ppc64] Compile failure in pass_v2sf (Illegal physical register for instruction)

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Thu Sep 27 11:03:58 PDT 2012 

http://llvm.org/bugs/show_bug.cgi?id=13954

             Bug #: 13954
           Summary: [ppc64] Compile failure in pass_v2sf (Illegal physical
                    register for instruction)
           Product: libraries
           Version: trunk
          Platform: Other
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: wschmidt at linux.vnet.ibm.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


For the 64-bit PowerPC SVR4 subtarget, one of the GCC ABI compatibility tests
encounters a compile failure in pass_v2sf, as follows:

spawn /home/wschmidt/llvm/install/llvm-base/bin/clang -w -DSKIP_DECIMAL_FLOAT
-DSKIP_DECIMAL_FLOAT -c -m64 -o c_compat_x_alt.o
/home/wschmidt/gcc/gcc-mainline-base/gcc/testsuite/gcc.dg/compat//vector-2_x.c

# In Register Scavenger
# Machine code for function pass_v2sf: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP-8]
  fi#0: size=8, align=8, at location [SP-16]
  fi#1: size=8, align=8, at location [SP-24]
  fi#2: size=4, align=4, at location [SP-28]
  fi#3: size=8, align=4, at location [SP-36]
  fi#4: size=16, align=16, at location [SP-64]
  fi#5: size=16, align=16, at location [SP-80]
  fi#6: size=4, align=4, at location [SP-84]
  fi#7: size=16, align=16, at location [SP-112]
  fi#8: size=8, align=8, at location [SP-120]
Function Live Ins: %V2 in %vreg0

BB#0: derived from LLVM BB %entry
    Live Ins: %V2
    %X0<def> = MFLR8 %LR8<imp-use>
    STD %X31, -2, %X1
    STD %X0, 4, %X1
    %X1<def,tied3> = STDU %X1, -60, %X1<tied0>
    %X31<def> = OR8 %X1, %X1
    %X5<def> = ADDI8 %X31, 160
    %X6<def> = ADDI8 %X31, 176
    STVX %V2, %X0, %X5; mem:ST16[FixedStack5]
    %X5<def> = LWZ8 4, %X5<kill>; mem:LD4[FixedStack5+4]
    STVX %V2, %X0, %X6<kill>; mem:ST16[FixedStack4]
    %X6<def> = LWZ8 176, %X31; mem:LD4[FixedStack4](align=16)
    %X5<def> = RLDICR %X5<kill>, 32, 31
    %X5<def> = OR8 %X6<kill>, %X5<kill>
    %R4<def> = LI 0
    STD %X5, 56, %X31; mem:ST8[%v.addr]
    STD %X5<kill>, 54, %X31; mem:ST8[%v1]
    STW %R4<kill>, 212, %X31; mem:ST4[%j]
    STW %R3<kill>, 156, %X31; mem:ST4[FixedStack6]
    %R0<def> = ADDI <fi#7>, 0
    STVX %V2<kill>, %R0, %R0; mem:ST16[FixedStack7]
    Successors according to CFG: BB#1

BB#1: derived from LLVM BB %for.cond
    Predecessors according to CFG: BB#0 BB#3
    %R3<def> = LWZ 0, <fi#2>; mem:LD4[%j]
    %CR0<def> = CMPWI %R3<kill>, 1
    BCC pred:44, pred:%CR0<kill>, <BB#4>
    B <BB#2>
    Successors according to CFG: BB#2(124) BB#4(4)

BB#2: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#1
    %X3<def> = LWA 0, <fi#2>; mem:LD4[%j]
    %X4<def> = ADDI8 <fi#1>, 0
    %X3<def> = RLDICR %X3<kill>, 2, 61
    %F0<def> = LFSX %X4<kill>, %X3; mem:LD4[%arrayidx]
    %X4<def> = ADDI8 <fi#3>, 0
    STFSX %F0<kill>, %X4<kill>, %X3<kill>; mem:ST4[%arrayidx4]
    Successors according to CFG: BB#3

BB#3: derived from LLVM BB %for.inc
    Predecessors according to CFG: BB#2
    %R3<def> = LWZ 0, <fi#2>; mem:LD4[%j]
    %R3<def> = ADDI %R3<kill>, 1
    STW %R3<kill>, 0, <fi#2>; mem:ST4[%j]
    B <BB#1>
    Successors according to CFG: BB#1

BB#4: derived from LLVM BB %for.end
    Predecessors according to CFG: BB#1
    %X3<def> = ADDI8 <fi#3>, 0
    BL8_NOP_ELF <ga:@checkp_2sf>, <regmask>, %LR8<imp-def,dead>, %RM<imp-use>,
%X3<imp-use,kill>, %R1<imp-def>
    %R4<def> = LWZ 0, <fi#6>; mem:LD4[FixedStack6]
    %X1<def> = ADDI8 %X1, 240
    %X0<def> = LD 4, %X1
    %X31<def> = LD -2, %X1
    MTLR8 %X0, %LR8<imp-def>
    BLR pred:20, pred:%noreg, %LR<imp-use>, %RM<imp-use>

# End machine code for function pass_v2sf.

*** Bad machine code: Using an undefined physical register ***
- function:    pass_v2sf
- basic block: BB#0 entry (0x12d9e9e0)
- instruction: STW %R3<kill>, 156, %X31; mem:ST4[FixedStack6]
- operand 0:   %R3<kill>

*** Bad machine code: Illegal physical register for instruction ***
- function:    pass_v2sf
- basic block: BB#0 entry (0x12d9e9e0)
- instruction: STVX %V2<kill>, %R0, %R0; mem:ST16[FixedStack7]
- operand 1:   %R0
R0 is not a G8RC register.

*** Bad machine code: Illegal physical register for instruction ***
- function:    pass_v2sf
- basic block: BB#0 entry (0x12d9e9e0)
- instruction: STVX %V2<kill>, %R0, %R0; mem:ST16[FixedStack7]
- operand 2:   %R0
R0 is not a G8RC register.
fatal error: error in backend: Found 3 machine code
errors.
compiler exited with status 1
output is:

# In Register Scavenger
# Machine code for function pass_v2sf: Post SSA
Frame Objects:
  fi#-1: size=8, align=8, fixed, at location [SP-8]
  fi#0: size=8, align=8, at location [SP-16]
  fi#1: size=8, align=8, at location [SP-24]
  fi#2: size=4, align=4, at location [SP-28]
  fi#3: size=8, align=4, at location [SP-36]
  fi#4: size=16, align=16, at location [SP-64]
  fi#5: size=16, align=16, at location [SP-80]
  fi#6: size=4, align=4, at location [SP-84]
  fi#7: size=16, align=16, at location [SP-112]
  fi#8: size=8, align=8, at location [SP-120]
Function Live Ins: %V2 in %vreg0

BB#0: derived from LLVM BB %entry
    Live Ins: %V2
    %X0<def> = MFLR8 %LR8<imp-use>
    STD %X31, -2, %X1
    STD %X0, 4, %X1
    %X1<def,tied3> = STDU %X1, -60, %X1<tied0>
    %X31<def> = OR8 %X1, %X1
    %X5<def> = ADDI8 %X31, 160
    %X6<def> = ADDI8 %X31, 176
    STVX %V2, %X0, %X5; mem:ST16[FixedStack5]
    %X5<def> = LWZ8 4, %X5<kill>; mem:LD4[FixedStack5+4]
    STVX %V2, %X0, %X6<kill>; mem:ST16[FixedStack4]
    %X6<def> = LWZ8 176, %X31; mem:LD4[FixedStack4](align=16)
    %X5<def> = RLDICR %X5<kill>, 32, 31
    %X5<def> = OR8 %X6<kill>, %X5<kill>
    %R4<def> = LI 0
    STD %X5, 56, %X31; mem:ST8[%v.addr]
    STD %X5<kill>, 54, %X31; mem:ST8[%v1]
    STW %R4<kill>, 212, %X31; mem:ST4[%j]
    STW %R3<kill>, 156, %X31; mem:ST4[FixedStack6]
    %R0<def> = ADDI <fi#7>, 0
    STVX %V2<kill>, %R0, %R0; mem:ST16[FixedStack7]
    Successors according to CFG: BB#1

BB#1: derived from LLVM BB %for.cond
    Predecessors according to CFG: BB#0 BB#3
    %R3<def> = LWZ 0, <fi#2>; mem:LD4[%j]
    %CR0<def> = CMPWI %R3<kill>, 1
    BCC pred:44, pred:%CR0<kill>, <BB#4>
    B <BB#2>
    Successors according to CFG: BB#2(124) BB#4(4)

BB#2: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#1
    %X3<def> = LWA 0, <fi#2>; mem:LD4[%j]
    %X4<def> = ADDI8 <fi#1>, 0
    %X3<def> = RLDICR %X3<kill>, 2, 61
    %F0<def> = LFSX %X4<kill>, %X3; mem:LD4[%arrayidx]
    %X4<def> = ADDI8 <fi#3>, 0
    STFSX %F0<kill>, %X4<kill>, %X3<kill>; mem:ST4[%arrayidx4]
    Successors according to CFG: BB#3

BB#3: derived from LLVM BB %for.inc
    Predecessors according to CFG: BB#2
    %R3<def> = LWZ 0, <fi#2>; mem:LD4[%j]
    %R3<def> = ADDI %R3<kill>, 1
    STW %R3<kill>, 0, <fi#2>; mem:ST4[%j]
    B <BB#1>
    Successors according to CFG: BB#1

BB#4: derived from LLVM BB %for.end
    Predecessors according to CFG: BB#1
    %X3<def> = ADDI8 <fi#3>, 0
    BL8_NOP_ELF <ga:@checkp_2sf>, <regmask>, %LR8<imp-def,dead>, %RM<imp-use>,
%X3<imp-use,kill>, %R1<imp-def>
    %R4<def> = LWZ 0, <fi#6>; mem:LD4[FixedStack6]
    %X1<def> = ADDI8 %X1, 240
    %X0<def> = LD 4, %X1
    %X31<def> = LD -2, %X1
    MTLR8 %X0, %LR8<imp-def>
    BLR pred:20, pred:%noreg, %LR<imp-use>, %RM<imp-use>

# End machine code for function pass_v2sf.

*** Bad machine code: Using an undefined physical register ***
- function:    pass_v2sf
- basic block: BB#0 entry (0x12d9e9e0)
- instruction: STW %R3<kill>, 156, %X31; mem:ST4[FixedStack6]
- operand 0:   %R3<kill>

*** Bad machine code: Illegal physical register for instruction ***
- function:    pass_v2sf
- basic block: BB#0 entry (0x12d9e9e0)
- instruction: STVX %V2<kill>, %R0, %R0; mem:ST16[FixedStack7]
- operand 1:   %R0
R0 is not a G8RC register.

*** Bad machine code: Illegal physical register for instruction ***
- function:    pass_v2sf
- basic block: BB#0 entry (0x12d9e9e0)
- instruction: STVX %V2<kill>, %R0, %R0; mem:ST16[FixedStack7]
- operand 2:   %R0
R0 is not a G8RC register.
fatal error: error in backend: Found 3 machine code
errors.

FAIL: gcc.dg/compat/vector-2 c_compat_x_alt.o compile

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