[LLVMbugs] [Bug 13938] New: Error selecting vduplane instruction for ARM

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Wed Sep 26 15:16:17 PDT 2012


             Bug #: 13938
           Summary: Error selecting vduplane instruction for ARM
           Product: tools
           Version: trunk
          Platform: PC
        OS/Version: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llc
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: dpeixott at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 9270
  --> http://llvm.org/bugs/attachment.cgi?id=9270

Compiling the following bitcode with  llc -march=arm -mattr=+neon

define <2 x float> @check_f32(<4 x float> %v) nounwind {
  %x = extractelement <4 x float> %v, i32 3
  %1 = insertelement  <2 x float> undef, float %x, i32 0
  %2 = insertelement  <2 x float> %1, float %x, i32 1
  ret <2 x float> %2

LLVM ERROR: Cannot select: 0x3753400: v2f32 = ARMISD::VDUPLANE 0x3752700,
0x3752800 [ID=16]
  0x3752700: v4f32 = bitcast 0x3752900 [ORD=1] [ID=15]
    0x3752900: v2f64 = ARMISD::BUILD_VECTOR 0x3751ac0, 0x3751fc0 [ID=14]
      0x3751ac0: f64 = ARMISD::VMOVDRR 0x37517c0, 0x37519c0 [ORD=1] [ID=12]
        0x37517c0: i32,ch = CopyFromReg 0x371f3b0, 0x37516c0 [ORD=1] [ID=8]
          0x37516c0: i32 = Register %vreg0 [ORD=1] [ID=1]
        0x37519c0: i32,ch = CopyFromReg 0x371f3b0, 0x37518c0 [ORD=1] [ID=9]
          0x37518c0: i32 = Register %vreg1 [ORD=1] [ID=2]
      0x3751fc0: f64 = ARMISD::VMOVDRR 0x3751cc0, 0x3751ec0 [ORD=1] [ID=13]
        0x3751cc0: i32,ch = CopyFromReg 0x371f3b0, 0x3751bc0 [ORD=1] [ID=10]
          0x3751bc0: i32 = Register %vreg2 [ORD=1] [ID=3]
        0x3751ec0: i32,ch = CopyFromReg 0x371f3b0, 0x3751dc0 [ORD=1] [ID=11]
          0x3751dc0: i32 = Register %vreg3 [ORD=1] [ID=4]
  0x3752800: i32 = Constant<3> [ORD=1] [ID=5]
In function: check_f32

The problem is there are no selection patterns for duplicating from a larger
vector into a narrower vector (e.g. from a lane of a Q register into a D

Attached a patch that adds new selection patterns for this case.

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