[LLVMbugs] [Bug 14079] New: Assertion in RegisterScavenger
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Sat Oct 13 02:47:24 PDT 2012
http://llvm.org/bugs/show_bug.cgi?id=14079
Bug #: 14079
Summary: Assertion in RegisterScavenger
Product: libraries
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: ARM
AssignedTo: unassignedbugs at nondot.org
ReportedBy: asl at math.spbu.ru
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
Created attachment 9344
--> http://llvm.org/bugs/attachment.cgi?id=9344
Testcase
Consider the attached testcase. Running llc on yields an (almost) assertion in
RegisterScavenger:
$ llc bugpoint-reduced-simplified.ll
# In Register Scavenger
# Machine code for function wombat: Post SSA
Function Live Outs: %Q0 %Q1 %Q2 %Q3
BB#0: derived from LLVM BB %bb
%Q8<def> = VMOVv4i32 0, pred:14, pred:%noreg
%D18<def> = VMOVv2i32 0, pred:14, pred:%noreg
%D16<def,tied2>, %D18<def,tied3> = VTRNd32 %D16<tied0>, %D18<kill,tied1>,
pred:14, pred:%noreg, %Q8<imp-use,kill>, %Q8<imp-def,dead>
%D4<def> = COPY %D17, %Q8<imp-use,kill>, %Q2<imp-def>
%D3<def> = VDUPLN32d %D18<kill>, 1, pred:14, pred:%noreg, %Q1<imp-def>
%Q0<def> = IMPLICIT_DEF
%Q3<def> = IMPLICIT_DEF
tBX_RET pred:14, pred:%noreg, %Q0<imp-use,kill>, %Q1<imp-use>,
%Q2<imp-use>, %Q3<imp-use,kill>
# End machine code for function wombat.
*** Bad machine code: Using an undefined physical register ***
- function: wombat
- basic block: BB#0 bb (0x7fc0e182a5c0)
- instruction: %D4<def> = COPY %D17, %Q8<imp-use,kill>, %Q2<imp-def>
- operand 1: %D17
*** Bad machine code: Using an undefined physical register ***
- function: wombat
- basic block: BB#0 bb (0x7fc0e182a5c0)
- instruction: %D4<def> = COPY %D17, %Q8<imp-use,kill>, %Q2<imp-def>
- operand 2: %Q8<imp-use,kill>
LLVM ERROR: Found 2 machine code errors.
And indeed, noone defines D17. It seems this goes from incorrect COPY
elimination. Before RA we have:
16B %vreg3<def> = VMOVv4i32 0, pred:14, pred:%noreg; QPR:%vreg3
32B %vreg7<def> = VMOVv2i32 0, pred:14, pred:%noreg; DPR:%vreg7
96B %vreg3:dsub_0<def,dead,tied2>, %vreg7<def,tied3> = VTRNd32
%vreg3:dsub_0<kill,tied0>, %vreg7<kill,tied1>, pred:14, pred:%noreg; QPR:%vreg3
DPR:%vreg7
112B %vreg10:dsub_0<def,read-undef> = COPY %vreg3:dsub_1<kill>;
QPR:%vreg10,%vreg3
128B %vreg13:dsub_1<def,read-undef> = VDUPLN32d %vreg7<kill>, 1,
pred:14, pred:%noreg; QPR:%vreg13 DPR:%vreg7
144B %Q0<def> = IMPLICIT_DEF
160B %Q1<def> = COPY %vreg13<kill>; QPR:%vreg13
176B %Q2<def> = COPY %vreg10<kill>; QPR:%vreg10
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