[LLVMbugs] [Bug 14359] New: ARM backend should generate vabs q, q for v4f32 vector type

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=14359

             Bug #: 14359
           Summary: ARM backend should generate vabs q, q for v4f32 vector
                    type
           Product: tools
           Version: trunk
          Platform: PC
        OS/Version: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llc
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: dpeixott at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


Currently, the ARM backend marks the FABS as EXPAND for the v4f32 type. For the
following bitcode:

define <4 x float> @test(<4 x float> %a) {
  %foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
  ret <4 x float> %foo
}
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)

We will generate:

        vmov    d1, r2, r3
        vmov    d0, r0, r1
        vabs.f32        s7, s3
        vabs.f32        s6, s2
        vabs.f32        s5, s1
        vabs.f32        s4, s0
        vmov    r0, r1, d2
        vmov    r2, r3, d3

It would be better to generate the vector version of vabs.f32 using a Q
register. Something like:

        vmov    d1, r2, r3
        vmov    d0, r0, r1
        vabs.f32        q1, q0
        vmov    r0, r1, d2
        vmov    r2, r3, d3


We need to improve the instruction selector to generate these instructions.
Without the EXPAND directive for v4f32, the instruction selector crashes. See
more discussion at:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/156031.html

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