[LLVMbugs] [Bug 12829] New: CriticalAntiDepBreaker rewrites a register operand of a call instruction

Mon May 14 18:06:25 PDT 2012

http://llvm.org/bugs/show_bug.cgi?id=12829

             Bug #: 12829
           Summary: CriticalAntiDepBreaker rewrites a register operand of
                    a call instruction
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: ahatanak at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 8561
  --> http://llvm.org/bugs/attachment.cgi?id=8561
bitcode file

This bug was discussed in the following llvm-dev thread:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-April/049132.html

When macroblock.ll is compiled, CriticalAntiDepBreaker changes the first
operand of JALR (an instruction for function calls) from T9 to S6.

(before)
JALR %T9<kill>, %A0<kill>, %A1<kill>, %A2<kill>, %A3<kill>, %GP<kill>,
<regmask>, %SP<imp-def>, %V0<imp-def>

(after)
JALR %S6<kill>, %A0<kill>, %A1<kill>, %A2<kill>, %A3<kill>, %GP<kill>,
<regmask>, %SP<imp-def>, %V0<imp-def>

This is incorrect. The first operand of JALR is supposed to be T9.

The problem can be reproduced by compiling the attached bitcode (macroblock.ll)
with the following gdb commands shown below. The current revision number is
r156768.

(gdb) b PostRASchedulerList.cpp:326
Breakpoint 1 at 0xf0dd84: file lib/CodeGen/PostRASchedulerList.cpp, line 326.
(gdb) condition 1 ((MI->getOpcode()==194) & ((*MBB).getNumber()==196))
(gdb) r macroblock.ll -O3 -o -
Breakpoint 1, runOnMachineFunction (this=0x222ad90, Fn=...)
    at lib/CodeGen/PostRASchedulerList.cpp:326
326            Scheduler.Observe(MI, CurrentCount);

(gdb) p MI->dump()
  JALR %T9<kill>, %A0<kill>, %A1<kill>, %A2<kill>, %A3<kill>, %GP<kill>,
<regmask>, %SP<imp-def>, %V0<imp-def>
$1 = void

This is the Machine BB dump before anti-dep breaker changes the register
operand:

(gdb) p (*MBB).dump()
BB#196: derived from LLVM BB %if.then1126
    Live Ins: %A1 %A2 %FP %GP %S1 %S3 %S4 %T0 %T5 %T7 %T8 %T9
    Predecessors according to CFG: BB#195
    SW %A1<kill>, %SP, 220; mem:ST4[FixedStack16]
    SW %T9, %SP, 16; mem:ST4[FixedStack-31](align=8)
    SW %T9<kill>, %SP, 244; mem:ST4[FixedStack10]
    %A3<def> = ADDu %ZERO, %T5<kill>
    SW %A3, %SP, 228; mem:ST4[FixedStack14]
    %T9<def> = LW %GP, <ga:@intrapred>[TF=3]; mem:LD4[GOT]
    %A0<def> = ADDu %ZERO, %S1
    %A1<def> = ADDu %ZERO, %A2
    SW %A2<kill>, %SP, 236; mem:ST4[FixedStack12]
    %A2<def> = ADDu %ZERO, %T0
    %S0<def> = ADDu %ZERO, %T0<kill>
    %S2<def> = ADDu %ZERO, %T8<kill>
    %S5<def> = ADDu %ZERO, %T7<kill>
    JALR %T9<kill>, %A0<kill>, %A1<kill>, %A2<kill>, %A3<kill>, %GP<kill>,
<regmask>, %SP<imp-def>, %V0<imp-def>
        ...

Now, set DebugFlag and continue:

(gdb) set DebugFlag=1
(gdb) b 339
(gdb) c
Continuing.
Critical path has total latency 3
Available regs: NOREG AT AT_64 D0 D0_64 D1 D1_64 D2 D2_64 D3 D3_64 D4 D4_64 D5
D5_64 D6 D6_64 D7 D7_64 D8 D8_64 D9 D9_64 D10_64 D11_64 D12_64 D13_64 D14_64
D15_64 D16_64 D17_64 D18_64 D19_64 D20_64 D21_64 D22_64 D23_64 D24_64 D25_64
D26_64 D27_64 D28_64 D29_64 D30_64 D31_64 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11
F12 F13 F14 F15 F16 F17 F18 F19 FCR31 FP_64 HI HI64 HWR29 HWR29_64 K0 K0_64 K1
K1_64 LO LO64 RA RA_64 S0_64 S1_64 S2_64 S3_64 S4_64 S5_64 S6 S6_64 S7 S7_64 SP
SP_64 T0 T0_64 T1 T1_64 T2 T2_64 T3 T3_64 T4 T4_64 T5 T5_64 T6 T6_64 T7 T7_64
T8 T8_64 V0 V0_64 V1 V1_64 ZERO ZERO_64
Breaking anti-dependence edge on T9 with 2 references using S6!
...

Breakpoint 2, runOnMachineFunction (this=0x222ad90, Fn=...)
    at lib/CodeGen/PostRASchedulerList.cpp:339
339        Scheduler.EmitSchedule();
(gdb) p (*MBB).dump()
BB#196: derived from LLVM BB %if.then1126
    Live Ins: %A1 %A2 %FP %GP %S1 %S3 %S4 %T0 %T5 %T7 %T8 %T9
    Predecessors according to CFG: BB#195
    SW %A1<kill>, %SP, 220; mem:ST4[FixedStack16]
    SW %T9, %SP, 16; mem:ST4[FixedStack-31](align=8)
    SW %T9<kill>, %SP, 244; mem:ST4[FixedStack10]
    %A3<def> = ADDu %ZERO, %T5<kill>
    SW %A3, %SP, 228; mem:ST4[FixedStack14]
    %S6<def> = LW %GP, <ga:@intrapred>[TF=3]; mem:LD4[GOT]
    %A0<def> = ADDu %ZERO, %S1
    %A1<def> = ADDu %ZERO, %A2
    SW %A2<kill>, %SP, 236; mem:ST4[FixedStack12]
    %A2<def> = ADDu %ZERO, %T0
    %S0<def> = ADDu %ZERO, %T0<kill>
    %S2<def> = ADDu %ZERO, %T8<kill>
    %S5<def> = ADDu %ZERO, %T7<kill>
    JALR %S6<kill>, %A0<kill>, %A1<kill>, %A2<kill>, %A3<kill>, %GP<kill>,
<regmask>, %SP<imp-def>, %V0<imp-def>
        ...

The first operand of JALR has been changed to S6 from T9.

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