[LLVMbugs] [Bug 12418] New: Missed CSE of div+rem

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=12418

             Bug #: 12418
           Summary: Missed CSE of div+rem
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: benny.kra at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


For this test case

---8<---

void foo(void);

void test(unsigned int x, unsigned int y, unsigned int q, unsigned int r) {
  if ((x / y) != q || (x % y) != r)
    foo();
}

--->8---

The x86-64 asm generated by clang -O3 looks like this:

_test:                                  ## @test
    .cfi_startproc
## BB#0:                                ## %entry
    movl    %edx, %r8d
    movl    %edi, %eax
    xorl    %edx, %edx
    divl    %esi
    cmpl    %r8d, %eax
    jne    LBB0_3
## BB#1:                                ## %lor.lhs.false
    movl    %edi, %eax
    xorl    %edx, %edx
    divl    %esi
    cmpl    %ecx, %edx
    jne    LBB0_3
## BB#2:                                ## %if.end
    ret
LBB0_3:                                 ## %if.then
    jmp    _foo                    ## TAILCALL

There should be only one "divl" as it can compute div and rem in one go. On ARM
we generate a call to __udivsi3 and to __umodsi3, not sure if there is a
libcall that handles both but if there is it would be twice as fast.

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