[LLVMbugs] [Bug 13254] New: scalarrepl wrong vector simplification

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=13254

             Bug #: 13254
           Summary: scalarrepl wrong vector simplification
           Product: new-bugs
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: baldrick at free.fr
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


opt -scalarrepl wrongly discards the store to the second half of the alloca.

target datalayout =
"e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"

define i64 @foo(<4 x i64> %x, <4 x i64> %y, i64 %n) {
  %tmp = alloca { <4 x i64>, <4 x i64> }
  %p0 = getelementptr inbounds { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 0
  store <4 x i64> %x, <4 x i64>* %p0
  %p1 = getelementptr inbounds { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 1
  store <4 x i64> %y, <4 x i64>* %p1
  %addr = getelementptr inbounds { <4 x i64>, <4 x i64> }* %tmp, i32 0, i32 0,
i64 %n
  %res = load i64* %addr, align 4
  ret i64 %res
}

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