[LLVMbugs] [Bug 13709] New: [Hexagon] LLVM generates needless SRL instruction to access the high register of a register pair.

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=13709

             Bug #: 13709
           Summary: [Hexagon] LLVM generates needless SRL instruction to
                    access the high register of a register pair.
           Product: tools
           Version: trunk
          Platform: PC
        OS/Version: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llc
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: pranavb at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


Created attachment 9115
  --> http://llvm.org/bugs/attachment.cgi?id=9115
Testcase to reproduce this problem.

Hexagon has 64 bit register pairs with 32 bit sub-registers. The 32bit high
word of a register pair can be used as a 32 bit register. However, LLVM
generates an SRL to access the upper 32 bits.

See attached testcase.
$> llc -march=hexagon -mcpu=hexagonv4 < remove_lsr.ll
............
.LBB0_1:                                // %for.body
                                        // =>This Inner Loop Header: Depth=1
      {
        r13 = sxtb(r13)
        r11:10 = vsubh(r7:6, r9:8):sat
        r12 = sxtb(r12)
      }
      {
        p0 = r13  /* Should almost never emit this. */
        r15:14 = lsr(r9:8, #32)
      }
      {
        r17:16 = lsr(r11:10, #32)
        r8 = mux(p0, r8, r10) 
        memw(r1++#4) = r8.new
        p0 = r12  /* Should almost never emit this. */
      }
      {
        r9 = mux(p0, r14, r16) <<< - Use r9 for r14 and r11 for r16.
        r8 = add(r4, r5)
        memw(r2++#4) = r9.new
      }

.............

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