[LLVMbugs] [Bug 13562] New: ARM eabi: 8-byte aligned structure passed in odd-even register pair

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Wed Aug 8 17:04:04 PDT 2012


http://llvm.org/bugs/show_bug.cgi?id=13562

             Bug #: 13562
           Summary: ARM eabi: 8-byte aligned structure passed in odd-even
                    register pair
           Product: clang
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: LLVM Codegen
        AssignedTo: unassignedclangbugs at nondot.org
        ReportedBy: ahatanak at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


Created attachment 9019
  --> http://llvm.org/bugs/attachment.cgi?id=9019
source file

This bug was discussed here:

http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-August/052378.html

$ clang  -target arm-none-linux-gnueabi-gcc  -ccc-clang-archs armv7
vararg1-main.c  -S -o vararg1-main.s -O3

In function "main", structure "s0" is being passed in register r1 and r2.
ARM EABI requires that arguments with double-word alignment (8-byte) be passed
in even-odd register pairs, so in this example, "s0" should be passed in r2 and
r3.

$ cat vararg1-main.s
...
  ldr r0, .LCPI0_0
  mov r11, sp
  ldm r0, {r1, r2}
  mov r0, #1
  bl  foo0
...
.LCPI0_0:
  .long .Lmain.s0
...
.Lmain.s0:
  .long 0
  .long 1073741824
  .size .Lmain.s0, 8


The bug seems to be in clang.

The ARM backend cannot tell argument "%0" has to be 8-byte aligned, because
type %struct.S0 is coerced to type [2 x i32] by clang: 

tail call arm_aapcscc  void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwind

Either coercing to type %struct.S0 to type [1 x i64] or inserting a dummy i32
argument before %0 solves the problem.

tail call arm_aapcscc  void (i32, ...)* @foo0(i32 1, [1 x i64] %0) nounwind
tail call arm_aapcscc  void (i32, ...)* @foo0(i32 1, i32 undef, [2 x i32] %0)
nounwind

$ cat vararg1-main.s

    ldr    r0, .LCPI0_0
    ldm    r0, {r2, r3}
    mov    r0, #1
    bl    foo0

-- 
Configure bugmail: http://llvm.org/bugs/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are on the CC list for the bug.



More information about the llvm-bugs mailing list