[LLVMbugs] [Bug 10960] New: [x86 disassembler] pop operand not displayed as expected for intel syntax

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=10960

           Summary: [x86 disassembler] pop operand not displayed as
                    expected for intel syntax
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: kkhoo at perfwizard.com
                CC: llvmbugs at cs.uiuc.edu


$ echo '0x0f 0xa1'| ./llvm-mc -disassemble -triple="x86_64"
-x86-asm-syntax=intel
    pop    %fs

$ echo '0x0f 0xa9'| ./llvm-mc -disassemble -triple="x86_64"
-x86-asm-syntax=intel
    pop    %gs

Based on how the disassembler treats other x86 registers, I would expect the
operand in these cases to be shown as "FS" and "GS" using Intel syntax  

For example:
$ echo '0x8f 0xc0'| ./llvm-mc -disassemble -triple="x86_64"
-x86-asm-syntax=intel
    pop    RAX
$ echo '0x8f 0xc0'| ./llvm-mc -disassemble -triple="x86_64"    popq    %rax


The cases below are similar, but these forms should all be invalid in x86-64
mode according to the Intel ISA reference: 
$ echo '0x1f'| ./llvm-mc -disassemble -triple="x86_64" -x86-asm-syntax=intel
    pop    %ds
$ echo '0x07'| ./llvm-mc -disassemble -triple="x86_64" -x86-asm-syntax=intel
    pop    %es
$ echo '0x17'| ./llvm-mc -disassemble -triple="x86_64" -x86-asm-syntax=intel
    pop    %ss

So these could be added as test cases for bug 10664.

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