[LLVMbugs] [Bug 11132] New: Missing %EFLAGS<kill> flag on CMOV causes suboptimal code

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=11132

           Summary: Missing %EFLAGS<kill> flag on CMOV causes suboptimal
                    code
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: stoklund at 2pi.dk
                CC: llvmbugs at cs.uiuc.edu


The unit test test/CodeGen/X86/uint64-to-float.ll generates this code:


# After Instruction Selection:
# Machine code for function test:
Function Live Ins: %RDI in %vreg0
Function Live Outs: %XMM0

BB#0: derived from LLVM BB %entry
    Live Ins: %RDI
    %vreg0<def> = COPY %RDI; GR64:%vreg0
    %vreg1<def> = SHR64r1 %vreg0, %EFLAGS<imp-def,dead>; GR64:%vreg1,%vreg0
    %vreg2<def> = AND64ri8 %vreg0, 1, %EFLAGS<imp-def,dead>; GR64:%vreg2,%vreg0
    %vreg3<def> = OR64rr %vreg2, %vreg1<kill>, %EFLAGS<imp-def,dead>;
GR64:%vreg3,%vreg2,%vreg1
    %vreg4<def> = CVTSI2SS64rr %vreg3<kill>; FR32:%vreg4 GR64:%vreg3
    %vreg5<def> = ADDSSrr %vreg4, %vreg4; FR32:%vreg5,%vreg4,%vreg4
    %vreg6<def> = CVTSI2SS64rr %vreg0; FR32:%vreg6 GR64:%vreg0
    TEST64rr %vreg0, %vreg0, %EFLAGS<imp-def>; GR64:%vreg0
    %vreg7<def> = CMOV_FR32 %vreg6<kill>, %vreg5<kill>, 15, %EFLAGS<imp-use>;
FR32:%vreg7,%vreg6,%vreg5
    %XMM0<def> = COPY %vreg7; FR32:%vreg7
    RET

Note the missing %EFLAGS<kill> flag on CMOV_FR32. When this instruction is
expanded by the custom inserter pass, the new blocks have %EFLAGS live-in
because of the missing kill flag:

# After Pre-RegAlloc TailDuplicate:
# Machine code for function test:
Function Live Ins: %RDI in %vreg0
Function Live Outs: %XMM0

BB#0: derived from LLVM BB %entry
    Live Ins: %RDI
    %vreg0<def> = COPY %RDI; GR64:%vreg0
    %vreg1<def> = SHR64r1 %vreg0, %EFLAGS<imp-def,dead>; GR64:%vreg1,%vreg0
    %vreg2<def> = AND64ri8 %vreg0, 1, %EFLAGS<imp-def,dead>; GR64:%vreg2,%vreg0
    %vreg3<def> = OR64rr %vreg2, %vreg1<kill>, %EFLAGS<imp-def,dead>;
GR64:%vreg3,%vreg2,%vreg1
    %vreg4<def> = CVTSI2SS64rr %vreg3<kill>; FR32:%vreg4 GR64:%vreg3
    %vreg5<def> = ADDSSrr %vreg4, %vreg4; FR32:%vreg5,%vreg4,%vreg4
    %vreg6<def> = CVTSI2SS64rr %vreg0; FR32:%vreg6 GR64:%vreg0
    TEST64rr %vreg0, %vreg0, %EFLAGS<imp-def>; GR64:%vreg0
    JS_4 <BB#2>, %EFLAGS<imp-use>
    Successors according to CFG: BB#1 BB#2

BB#1: derived from LLVM BB %entry
    Live Ins: %EFLAGS
    Predecessors according to CFG: BB#0
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %entry
    Live Ins: %EFLAGS
    Predecessors according to CFG: BB#0 BB#1
    %vreg7<def> = PHI %vreg6, <BB#1>, %vreg5, <BB#0>; FR32:%vreg7,%vreg6,%vreg5
    %XMM0<def> = COPY %vreg7; FR32:%vreg7
    RET

MachineSinking can split the critical edge, but it cannot sink the instructions
clobbering %EFLAGS into a block with %EFLAGS live-in.

All of this happens before the proper liveness analysis in LiveVariables, but
InstrEmitter could add a kill flag to %EFLAGS.

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