[LLVMbugs] [Bug 9955] New: MOVLPSmr incorrectly gets LD memory operands

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=9955

           Summary: MOVLPSmr incorrectly gets LD memory operands
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: zwarich at apple.com
                CC: llvmbugs at cs.uiuc.edu


I see these failures on CodeGen/X86/swizzle.ll and
CodeGen/X86/vec_shuffle-18.ll. This is a normal store, so it shouldn't be
getting a LD operand.

******************** TEST 'LLVM :: CodeGen/X86/swizzle.ll' FAILED
********************
Script:
--
/Volumes/Data/b/Release+Asserts/bin/llc <
/Volumes/Data/l/test/CodeGen/X86/swizzle.ll -march=x86 -mattr=+sse2 | grep
movlps
/Volumes/Data/b/Release+Asserts/bin/llc <
/Volumes/Data/l/test/CodeGen/X86/swizzle.ll -march=x86 -mattr=+sse2 | grep
movsd
/Volumes/Data/b/Release+Asserts/bin/llc <
/Volumes/Data/l/test/CodeGen/X86/swizzle.ll -march=x86 -mattr=+sse2 |
/Volumes/Data/b/Release+Asserts/bin/not grep movups
--
Exit Code: 1
Command Output (stderr):
--

# Before register coalescing
# Machine code for function swizzle:
Frame Objects:
  fi#-3: size=4, align=8, fixed, at location [SP+12]
  fi#-2: size=4, align=4, fixed, at location [SP+8]
  fi#-1: size=4, align=16, fixed, at location [SP+4]

0L    BB#0: derived from LLVM BB %entry
16L        %vreg0<def> = MOV32rm <fi#-1>, 1, %noreg, 0, %noreg;
mem:LD4[FixedStack-1](align=16) GR32:%vreg0
32L        %vreg1<def> = MOVSDrm %vreg0<kill>, 1, %noreg, 0, %noreg;
mem:LD8[%tmp.i](align=4) FR64:%vreg1 GR32:%vreg0
48L        %vreg2<def> = SUBREG_TO_REG 0, %vreg1<kill>, 5; VR128:%vreg2
FR64:%vreg1
64L        %vreg3<def> = MOV32rm <fi#-2>, 1, %noreg, 0, %noreg;
mem:LD4[FixedStack-2] GR32:%vreg3
80L        MOVLPSmr %vreg3<kill>, 1, %noreg, 0, %noreg, %vreg2<kill>;
mem:ST16[%0](align=4) LD16[%0](align=4) GR32:%vreg3 VR128:%vreg2
96L        RET

# End machine code for function swizzle.

*** Bad machine code: Missing mayLoad flag ***
- function:    swizzle
- basic block: entry 0x7fa4e9833fa0 (BB#0) [0L;112L)
- instruction: 80L    MOVLPSmr %vreg3<kill>, 1, %noreg, 0, %noreg,
%vreg2<kill>; mem:ST16[%0](align=4) LD16[%0](align=4) GR32:%vreg3 VR128:%vreg2
LLVM ERROR: Found 1 machine code errors.
--

The patterns look like this:


def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
                   "movlps\t{$src, $dst|$dst, $src}",
                   [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
                                 (iPTR 0))), addr:$dst)]>, VEX;

Maybe it's the (iPTR 0) that is confusing it?

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