[LLVMbugs] [Bug 9176] New: ARM assertion failed when disassembling LDR & STR imm offset form

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=9176

           Summary: ARM assertion failed when disassembling LDR & STR imm
                    offset form
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: crabtw at gmail.com
                CC: llvmbugs at cs.uiuc.edu


Message for ldr r0, [r2, #32]:

================

$ echo '0x20 0x00 0x92 0xe5'|Debug+Asserts/bin/llvm-mc -arch=arm --disassemble
-debug
Args: Debug+Asserts/bin/llvm-mc -arch=arm --disassemble -debug
Opcode=163 Name=LDRi12 Format=ARM_FORMAT_LDFRM(6)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6 
5  4  3  2  1  0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 1: 0: 1| 1: 0: 0: 1| 0: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0:
1: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

llvm-mc:
/home/jyyou/src/llvm-trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp:1078:
bool DisassembleLdStFrm(llvm::MCInst&, unsigned int, uint32_t, short unsigned
int, unsigned int&, bool, llvm::ARMBasicMCBuilder*): Assertion
`(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) && (OpInfo[OpIdx+1].RegClass <
0) && "Expect 1 reg operand followed by 1 imm operand"' failed.

================

Pre-indexed and post-indexed have no problem.

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