[LLVMbugs] [Bug 11529] New: Tblgen type inference: Assertion failure
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Fri Dec 9 16:40:21 PST 2011
http://llvm.org/bugs/show_bug.cgi?id=11529
Bug #: 11529
Summary: Tblgen type inference: Assertion failure
Product: new-bugs
Version: trunk
Platform: PC
OS/Version: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: new bugs
AssignedTo: unassignedbugs at nondot.org
ReportedBy: ivanllopard at gmail.com
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
Hi,
I have got an assertion failure when tblgen tried to build the instruction
information description by analizyng the following patern:
def mul_add : MephInstr<(outs RARegs:$dst), (ins RARegs:$src, RARegs:$a,
RARegs:$b), "mulaa",
[(set RARegs:$dst, (insertelt RARegs:$src,
(i16 (trunc (add
(ncmul
(sext (extractelt RARegs:$a, imm)),
(sext (extractelt RARegs:$b, imm))
),
(ncmul
(sext (extractelt RARegs:$a, imm)),
(sext (extractelt RARegs:$b, imm))
)
))),
imm) )] >;
Where RARegs is the only register class I have defined with types [i32, v2i16].
Hereafter, the execution back-trace of tblgen:
llvm-tblgen: /llvm/include/llvm/ADT/SmallVector.h:150: T&
llvm::SmallVectorTemplateCommon<T>::operator[](unsigned int) [with T =
llvm::MVT::SimpleValueType, T& = llvm::MVT::SimpleValueType&]: Assertion
`begin() + idx < end()' failed.
0 llvm-tblgen 0x081c0e8a
1 llvm-tblgen 0x081c0c17
2 0x4001e400 __kernel_sigreturn + 0
3 libc.so.6 0x401af34e abort + 382
4 libc.so.6 0x401a4888 __assert_fail + 248
5 llvm-tblgen 0x080a7692
6 llvm-tblgen 0x0809319d
7 llvm-tblgen 0x080955b7
8 llvm-tblgen 0x080a430b
9 llvm-tblgen 0x08098c3e
10 llvm-tblgen 0x08098c8b
11 llvm-tblgen 0x08098c8b
12 llvm-tblgen 0x08098c8b
13 llvm-tblgen 0x08098c8b
14 llvm-tblgen 0x080982a1
15 llvm-tblgen 0x0809b9ad
16 llvm-tblgen 0x0809f770
17 llvm-tblgen 0x0809c2c2
18 llvm-tblgen 0x08164b8c
19 llvm-tblgen 0x08165197
20 llvm-tblgen 0x08171aac
21 llvm-tblgen 0x0816458c
22 libc.so.6 0x40197e37 __libc_start_main + 231
23 llvm-tblgen 0x0804c411
Stack dump:
0. Program arguments: /llvm/_build/Debug+Asserts/bin/llvm-tblgen -I
/llvm/lib/Target/Meph -I /llvm/include -I /llvm/include -I /llvm/lib/Target
-gen-instr-info -o
/llvm/_build/lib/Target/Meph/Debug+Asserts/MephGenInstrInfo.inc.tmp
/llvm/lib/Target/Meph/Meph.td
Let me know if more information is needed.
Regards,
Ivan
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