[LLVMbugs] [Bug 10632] New: MC Assembler generates ARM NOP instructions instead of Thumb NOP instructions when aligning

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=10632

           Summary: MC Assembler generates ARM NOP instructions instead of
                    Thumb NOP instructions when aligning
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: kristof.beyls at gmail.com
                CC: llvmbugs at cs.uiuc.edu


The following assembler file gets mis-assembled:

$ cat ArmNopsInThumbCode.s
        .section        __TEXT //,__text,regular,pure_instructions
        .text
        .code   16
f:
$t:
        add     r0, r0, #1
.align 3
        add     r0, r0, #2
        bx      lr

When using the following command line:
$ build/Debug+Asserts/bin/llvm-mc -arch=thumb -mcpu=arm926ej-s
ArmNopsInThumbCode.s -filetype=obj -o ArmNopsInThumbCode.o

Disassembling the generated ELF file with GNU objdump shows that ARM NOP
instructions were generated instead of Thumb NOP instructions:


$ arm-none-eabi-objdump -d ArmNopsInThumbCode.o

ArmNopsInThumbCode.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <f>:
   0:   1c40            adds    r0, r0, #1
   2:   0000            movs    r0, r0
   4:   0e1a            lsrs    r2, r3, #24
   6:   0000            movs    r0, r0
   8:   1c80            adds    r0, r0, #2
   a:   4770            bx      lr


The decoded instruction at offsets 2-6 should be 16-bit Thumb NOP instructions.
However, when looking at the encoding "0000 0e1a 0000", it seems that the ARM
pseudo-NOP instruction (i.e. MOV r0,r0) was encoded.

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