[LLVMbugs] [Bug 8112] New: Missed optimization during register coalescing

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=8112

           Summary: Missed optimization during register coalescing
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Keywords: code-quality
          Severity: normal
          Priority: P
         Component: Register Allocator
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: borja.ferav at gmail.com
                CC: llvmbugs at cs.uiuc.edu


Compiling the following C code with:

$ clang -cc1 -triple thumbv5-u-u -S -O2 test.c -o -

typedef unsigned long long t;
t foo(t a, t b)
{
    t a4 = b^a^18;
    return a4;
}

emits:

    eors    r1, r3
    mov    r3, r0
    eors    r3, r2
    movs    r0, #18
    eors    r0, r3
    bx    lr

instead of

    eors    r1, r3
    eors    r0, r2
    movs    r4, #18
    eors    r0, r4
    bx    lr

IR:
define arm_aapcscc i64 @foo(i64 %a, i64 %b) nounwind readnone {
entry:
  %xor = xor i64 %a, 18                           ; <i64> [#uses=1]
  %xor2 = xor i64 %xor, %b                        ; <i64> [#uses=1]
  ret i64 %xor2
}

The first move could be eliminated if the imm value is moved to a scratch
register instead of moving it to r0 which is used as a return value register.

I noticed this while developing a new backend, however it can be reproduced in
ARM aswell (shown here), so it's not a backend issue.
Jakob Stoklund did a great analysis explaining where the problem is that can be
found here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-September/034430.html

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