[LLVMbugs] [Bug 8411] New: ARM back end is not very clever with shufflevector
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Mon Oct 18 09:29:20 PDT 2010
http://llvm.org/bugs/show_bug.cgi?id=8411
Summary: ARM back end is not very clever with shufflevector
Product: libraries
Version: trunk
Platform: PC
OS/Version: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: ARM
AssignedTo: unassignedbugs at nondot.org
ReportedBy: Edmund.Grimley-Evans at arm.com
CC: llvmbugs at cs.uiuc.edu
Created an attachment (id=5635)
--> (http://llvm.org/bugs/attachment.cgi?id=5635)
C source code for two functions that load a Q reg then store half of it
In gethalf.c (attached) there are two functions that load a Q reg then
store half of it.
The first function does it the way <arm_neon.h> implements
vget_low_s16: it goes via a vector of two float64s. The intermediate
LLVM assembler code uses extractelement and three bitcasts, and the
final assembler code is nice and simple:
f1:
vld1.16 {d16, d17}, [r1]
vst1.16 {d16}, [r0]
bx lr
The second function uses __builtin_shufflevector. The intermediate LLVM
assembler code is very simple: just a shufflevector. However, the final
assembler code is very bad: the shuffle is implemented by going via the
stack (and there are some redundant address calculations);
vld1.16 {d16, d17}, [r1]
mov r1, sp
vstmia r1, {d16, d17}
vldr.64 d16, [sp]
vst1.16 {d16}, [r0]
It would be nice if use of shufflevector would give good output code.
If you are dealing with code that has a lot of shuffles this is
probably the canonical way these operations will be represented.
The command lines were:
clang -cc1 -triple thumbv7-eabi -target-cpu cortex-a8 gethalf.c -O3 -emit-llvm
-o gethalf.ll
clang -cc1 -triple thumbv7-eabi -target-cpu cortex-a8 gethalf.c -O3 -S -o
gethalf.s
If you want to try it without Clang:
llc -mcpu cortex-a8 gethalf.ll -o gethalf.s
I'm at revision 116700.
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