[LLVMbugs] [Bug 7227] New: [ARM JIT] Missing the implementation of ARM::LEApcrel

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=7227

           Summary: [ARM JIT] Missing the implementation of ARM::LEApcrel
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: sliao at google.com
                CC: llvmbugs at cs.uiuc.edu


In the function "void ARMCodeEmitter::emitLEApcrelJTInstruction(const
MachineInstr &MI)", only "case ARM::LEApcrelJT:" is implemented. But "case
ARM::LEApcrel:" didn't get implemented. As a result, the PC relative addressing
to the constant pool in the following program doesn't work.

int main(int argc, char** argv) {
  if(argc == 10000) {
    int i;
    float ident[16];
    float masterscale = 0.0041f;// / (gXOffset * 4.f + 1.f);

    int now = argc;
    timedelta = ((float)(now - lastuptime)) / 44.f;
    lastuptime = now;
    if (timedelta > 3) {
        // Limit the step adjustment factor to 3, so we don't get a sudden jump
        // after coming back from sleep.
        timedelta = 3;
    }

    i = gPreset;
    if (i != currentpreset) {
        currentpreset = i;
        int rgb = gBackCol;
        makeTextures();
    }
  }

  if(argc > 1)
      gTextureSwap = 1;
  else
      gTextureSwap = 0;

  if (gTextureSwap != 0) 
      scale[0] = .25f;
  else 
      scale[0] = 4.f;

  printf("%d %f\n", gTextureSwap, scale[0]);
  return 55;
}

Note that the constants 0.25f and 4.f are in the constant pool. If we implement
the ARM::LEApcrel below, then the pc relative address will be correct. That is,
it will generate correct code here:
    0x400099c4: add r0, pc, #56 ; pc = 0x400099c8, pc + 56 = 0x40009a00
    0x400099c8: add r2, r0, #4
    0x400099cc: cmp r4, #2
    0x400099d0: movlt r2, r0
    0x400099d4: vldr.32 s0, [r2]
    0x400099d8: movw r0, #7977
    0x400099dc: movt r0, #16386
    0x400099e0: movw r2, #8000
    0x400099e4: movt r2, #16386
    0x400099e8: vstr.32 s0, [r2]
    0x400099ec: vcvt.f64.f32 d0, s0
    0x400099f0: vmov r2, r3, d0
    0x400099f4: bl #99620
    0x400099f8: mov r0, #55
    0x400099fc: pop {r4, pc} ; End of main()
    0x40009a00: eormis r0, r0, #0  ; Constant entry #1: 44.f
    0x40009a04: addmi r0, r0, r0   ; Constant entry #2[0]: 0.25f
    0x40009a08: cdplo p0, #8, cr0, cr0, cr0, #0 ; Constant entry #2[1]: 4.f

An implementation of ARM::LEApcrel is:

void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
  // It's basically add r, pc, (LCPI - $+8)

  const TargetInstrDesc &TID = MI.getDesc();

  // Emit the 'add' instruction.
  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100

  // For VFP load, the immediate offset is multiplied by 4.
  unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
   ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;

  // Set the conditional execution predicate
  Binary |= II->getPredicate(&MI) << ARMII::CondShift;

  // Encode S bit if MI modifies CPSR.
  Binary |= getAddrModeSBit(MI, TID);

  // Encode Rd.
  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;

  // Encode Rn which is PC.
  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) <<
ARMII::RegRnShift;

  // Encode the displacement.
  Binary |= 1 << ARMII::I_BitShift;
  emitConstPoolAddress(MI.getOperand(1).getIndex(), Reloc);

  emitWordLE(Binary);
}

This will fix all the remaining known issues in ARM JIT based on our test
suite.

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