[LLVMbugs] [Bug 7483] New: Useless zero-extends generated in RISC-like backend ?

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=7483

           Summary: Useless zero-extends generated in RISC-like backend ?
           Product: new-bugs
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: quickslyver at free.fr
                CC: llvmbugs at cs.uiuc.edu


First of all I don't know if it is a real bug, please change the status/Summary
of this bug I you know the answer!

-------------------------------
With the following C-code:

$ cat test.c
char g;

void test(char a,char b,char c)
{
  g=a+b-c;
}

char test2(char a,char b,char c)
{
  return a+b-c;
}

char test3(char a,char b,char c)
{
  g=a+b-c;
  return g;
}

--------------------------------
Compiled with clang the assembly code generated looks like with thumb target:
(without directives...)
$ clang -cc1 -triple=thumbv7-u-u test.c -S -o - -O3 -mrelocation-model static

test:
    adds    r0, r1, r0
    and    r1, r2, #255
    movw    r2, :lower16:g
    subs    r0, r0, r1
    movt    r2, :upper16:g
    strb    r0, [r2]
    bx    lr

test2:
    adds    r0, r1, r0
    subs    r0, r0, r2
    sbfx    r0, r0, #0, #8
    bx    lr

test3:
    and    r0, r0, #255
    and    r1, r1, #255
    adds    r0, r1, r0
    and    r1, r2, #255
    movw    r2, :lower16:g
    subs    r0, r0, r1
    movt    r2, :upper16:g
    strb    r0, [r2]
    sbfx    r0, r0, #0, #8
    bx    lr

--------------------
I think that all the 'and' instructions in "test" and "test3" functions are
useless. "test2" is correctly generated.
There is the same behavior with others Risc targets for example mips or arm

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