[LLVMbugs] [Bug 7277] New: Scheduler cannot issue multiple instructions per cycle

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=7277

           Summary: Scheduler cannot issue multiple instructions per cycle
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: asl at math.spbu.ru
                CC: llvmbugs at cs.uiuc.edu


Consider the following LLVM IR:

target datalayout =
"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv7-eabi"

@foo = common global i32* null, align 4           ; <i32**> [#uses=1]
@bar = common global i32* null, align 4           ; <i32**> [#uses=1]

define arm_aapcscc void @aaa() nounwind {
entry:
  %tmp = load i32** @foo                          ; <i32*> [#uses=1]
  %tmp1 = load i32** @bar                         ; <i32*> [#uses=1]
  call arm_aapcscc  void @baz(i32* %tmp, i32* %tmp1)
  ret void
}

declare arm_aapcscc void @baz(i32*, i32*)

llc -mcpu=cortex-a8 currently codegens this into (interesting part is shown):
        movw    r0, :lower16:foo
        movt    r0, :upper16:foo  (*)
        movw    r1, :lower16:bar (*)
        movt    r1, :upper16:bar
The running time of the code is 3 cycles at minimum since only (*) instructions
can be issued in parallel.

ARM can issue 2 instructions per cycle, thus the optimal code here is:
       movw    r0, :lower16:foo
       movw    r1, :lower16:bar
       movt    r0, :upper16:foo
       movt    r1, :upper16:bar

Up to 2 cycles can be saved here. Note that the pipeline description is
properly written for Cortex A8/A9 (and there is an indication of 2 functional
units available), so, this is definitely a scheduler deficiency.

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