[LLVMbugs] [Bug 7832] New: ARM Disassembler: BLX is variously disassembled as B or BL

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=7832

           Summary: ARM Disassembler: BLX is variously disassembled as B
                    or BL
           Product: new-bugs
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: sliedes at cc.hut.fi
                CC: llvmbugs at cs.uiuc.edu


(trunk r110360)

I think the ARM disassembler does not produce the BLX instruction ever.
Instead, it is variously (and wrongly) disassembled as B or BL.

B is defined as

  cond 1010 imm24

BL as

  cond 1011 imm24

and BLX as

  1111 101H imm24

There's no contradiction in this, because 1111 is not a valid condition code.

However, llvm-mc disassembles blx instructions as b or bl:

$ echo '0x3a 0x9f 0xb5 0xfa' |Release+Asserts/bin/llvm-mc --disassemble
--triple=arm
        b       #-19497744

(This is BLX 0xfed69dc8)

$ echo '0x00 0x00 0x68 0xfb' |Release+Asserts/bin/llvm-mc --disassemble
--triple=arm
        bl      #27262984

(This is BLX 0x1a02492)

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