[LLVMbugs] [Bug 5374] New: DAG Combiner inserts illegal nodes.

bugzilla-daemon at cs.uiuc.edu bugzilla-daemon at cs.uiuc.edu
Mon Nov 2 15:23:10 PST 2009


           Summary: DAG Combiner inserts illegal nodes.
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P2
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: tilmann.scheller at googlemail.com
                CC: llvmbugs at cs.uiuc.edu

TargetLowering::SimplifyDemandedBits() inserts nodes without checking whether
they are legal on the target or not.

I ran into this issue with a target which custom lowers srl.

E.g. on ppc32 the following LLVM IR:

define i32 @foo(i32 %A, i32 %B) {
        %r1 = xor i32 %B, -1
        %r2 = and i32 %r1, %A
        %r3 = sub i32 %A, %B
        %r4 = or i32 %A, %r1
        %r5 = and i32 %r3, %r4
        %r6 = or i32 %r5, %r2
        %r7 = ashr i32 %r6, 31
        %r8 = and i32 %r7, 1
        %r9 = xor i32 %r7, -1
        %r10 = and i32 %r9, 0
        %r11 = or i32 %r10, %r8
        %r12 = and i32 %r11, 1  
        ret i32 %r12

triggers the following optimization:

Replacing.2 0x2c44030: i32 = sra 0x2c43e40, 0x2c43f38
With: 0x2c44318: i32 = srl 0x2c43e40, 0x2c43f38

On ppc32 this transformation is valid, however on targets where slr is custom
lowered it is not.

The optimization is done at line 1227 of TargetLowering.cpp.

It seems that SimplifyDemandedBits() never checks whether it is allowed to
insert a certain node, so there are possibly many other ways to trigger this

Configure bugmail: http://llvm.org/bugs/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are on the CC list for the bug.

More information about the llvm-bugs mailing list