[LLVMbugs] [Bug 3826] New: InstComb assert with vector shift and no MMX generated

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=3826

           Summary: InstComb assert with vector shift and no MMX generated
           Product: new-bugs
           Version: unspecified
          Platform: PC
        OS/Version: Windows NT
            Status: NEW
          Severity: normal
          Priority: P2
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: nicolas at capens.net
                CC: llvmbugs at cs.uiuc.edu


The IR code below asserts in ValueTracking.cpp:566 (the first line of
llvm::ComputeNumSignBits) when using an instruction combining optimization
pass:

define internal void @0(<4 x i16>*, <4 x i16>*) {
        %3 = alloca <4 x i16>*          ; <<4 x i16>**> [#uses=2]
        %4 = alloca <4 x i16>*          ; <<4 x i16>**> [#uses=2]
        store <4 x i16>* %0, <4 x i16>** %4
        store <4 x i16>* %1, <4 x i16>** %3
        %5 = load <4 x i16>** %3                ; <<4 x i16>*> [#uses=1]
        %6 = load <4 x i16>* %5, align 1                ; <<4 x i16>> [#uses=1]
        %7 = lshr <4 x i16> %6, <i16 5, i16 5, i16 5, i16 5>            ; <<4 x
i16>> [#uses=1]
        %8 = load <4 x i16>** %4                ; <<4 x i16>*> [#uses=1]
        store <4 x i16> %7, <4 x i16>* %8, align 1
        ret void
}

The assert is about a cast to an incompatible type; as far as I can tell the
function doesn't expect a vector as the second argument of lshr.

Furthermore, this generates very inefficient scalar code with four x86 shr
instrutions, while it's supposed to be a perfect match for the MMX psrlw
instruction. I suspect it doesn't work for any MMX/SSE vector shift.


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