[LLVMbugs] [Bug 4657] New: register scavenger asserts with subreg lowering
bugzilla-daemon at cs.uiuc.edu
bugzilla-daemon at cs.uiuc.edu
Thu Jul 30 17:51:29 PDT 2009
http://llvm.org/bugs/show_bug.cgi?id=4657
Summary: register scavenger asserts with subreg lowering
Product: libraries
Version: trunk
Platform: Macintosh
OS/Version: MacOS X
Status: NEW
Severity: normal
Priority: P2
Component: Register Allocator
AssignedTo: unassignedbugs at nondot.org
ReportedBy: bob.wilson at apple.com
CC: llvmbugs at cs.uiuc.edu
Created an attachment (id=3262)
--> (http://llvm.org/bugs/attachment.cgi?id=3262)
testcase
The attached file causes the scavenger to assert when compiled with "llc
-march=arm -mattr=+neon". Here is what I think is happening. (I've actually
been looking at a slightly different case that doesn't occur without some of my
local changes, but I think it is the same problem.) A Neon quad register is
defined by a pair of insert_subregs. The subreg accesses are lowered into
copies that assign the underlying Neon double registers. Now you've got a quad
register that is used but never (directly) defined. Or, at least that seems to
be what the scavenger is thinking.
For example, in the following Q1 is defined:
%D0<def> = FMDRR %R2<kill>, %R3<kill>, 14, %reg0
%D1<def> = FMDRR %R0<kill>, %R1<kill>, 14, %reg0
%Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
%Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6
%R0<def> = ADDri <fi#0>, 0, 14, %reg0, %reg0
VSTRQ %Q1<kill>, %R0, Mem:ST(16,16) [v_addr + 0]
but then the INSERT_SUBREGs are lowered:
********** LOWERING SUBREG INSTRS **********
********** Function: scale
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
subreg: %D2<def> = FCPYD %D1, 14, %reg0
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6subreg: %D3<def>
= FCPYD %D0, 14, %reg0
and the scavenger asserts:
Assertion failed: (isUsed(Reg) && "Using an undefined register!"), function
forward, file
/Users/bwilson/local/llvm/llvm/lib/CodeGen/RegisterScavenging.cpp, line 221.
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