[LLVMbugs] [Bug 3624] New: Tablegen incorrectly transoforming a pattern

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=3624

           Summary: Tablegen incorrectly transoforming a pattern
           Product: tools
           Version: trunk
          Platform: PC
        OS/Version: Windows XP
            Status: NEW
          Severity: normal
          Priority: P2
         Component: TableGen
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: micah.villmow at amd.com
                CC: llvmbugs at cs.uiuc.edu


The following pattern:
def DIV_i32 : Pat<(sdiv GPRI32:$src0, GPRI32:$src1),
    (CMOVLOG_i32 
     (BINARY_AND_i32 
      (BINARY_XOR_i32 GPRI32:$src0, GPRI32:$src1), 
      (LOADCONST_i32 0x80000000)), 
     (NEGATE_i32 
      (UDIV_i32 
       (MAX_i32 GPRI32:$src0, 
        (NEGATE_i32 GPRI32:$src0)), 
       (MAX_i32 GPRI32:$src1, 
        (NEGATE_i32 GPRI32:$src1)))), 
     (UDIV_i32 
      (MAX_i32 GPRI32:$src0, 
       (NEGATE_i32 GPRI32:$src0)), 
      (MAX_i32 GPRI32:$src1, 
       (NEGATE_i32 GPRI32:$src1))))>; 

Is incorrectly transformed to:
SDNode *Emit_29(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2,
unsigned Opc3, unsigned Opc4, unsigned Opc5, unsigned Opc6, unsigned Opc7,
unsigned Opc8, unsigned Opc9, unsigned Opc10, unsigned Opc11, unsigned Opc12,
unsigned Opc13, unsigned Opc14, MVT VT0, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
MVT VT5, MVT VT6, MVT VT7, MVT VT8, MVT VT9, MVT VT10, MVT VT11, MVT VT12, MVT
VT13, MVT VT14) DISABLE_INLINE {
  SDValue N0 = N.getOperand(0);
  SDValue N1 = N.getOperand(1);
  AddToISelQueue(N0);
  AddToISelQueue(N1);
  SDValue Tmp2(CurDAG->getTargetNode(Opc0, VT0, N0, N1), 0);
  SDValue Tmp3 = CurDAG->getTargetConstant(0x7FFFFFFFULL, MVT::i32);
  SDValue Tmp4(CurDAG->getTargetNode(Opc1, VT1, Tmp3), 0);
  SDValue Tmp5(CurDAG->getTargetNode(Opc2, VT2, Tmp2, Tmp4), 0);
  AddToISelQueue(N0);
  AddToISelQueue(N0);
  SDValue Tmp8(CurDAG->getTargetNode(Opc3, VT3, N0), 0);
  SDValue Tmp9(CurDAG->getTargetNode(Opc4, VT4, N0, Tmp8), 0);
  AddToISelQueue(N1);
  AddToISelQueue(N1);
  SDValue Tmp12(CurDAG->getTargetNode(Opc5, VT5, N1), 0);
  SDValue Tmp13(CurDAG->getTargetNode(Opc6, VT6, N1, Tmp12), 0);
  SDValue Tmp14(CurDAG->getTargetNode(Opc7, VT7, Tmp9, Tmp13), 0);
  SDValue Tmp15(CurDAG->getTargetNode(Opc8, VT8, Tmp14), 0);
  AddToISelQueue(N0);
  AddToISelQueue(N0);
  SDValue Tmp18(CurDAG->getTargetNode(Opc9, VT9, N0), 0);
  SDValue Tmp19(CurDAG->getTargetNode(Opc10, VT10, N0, Tmp18), 0);
  AddToISelQueue(N1);
  AddToISelQueue(N1);
  SDValue Tmp22(CurDAG->getTargetNode(Opc11, VT11, N1), 0);
  SDValue Tmp23(CurDAG->getTargetNode(Opc12, VT12, N1, Tmp22), 0);
  SDValue Tmp24(CurDAG->getTargetNode(Opc13, VT13, Tmp19, Tmp23), 0);
  return CurDAG->SelectNodeTo(N.getNode(), Opc14, VT14, Tmp5, Tmp15, Tmp24);
}
SDNode *Select_ISD_SDIV_i32(const SDValue &N) {
  return Emit_29(N, AMDIL::BINARY_XOR_i32, AMDIL::LOADCONST_i32,
AMDIL::BINARY_AND_i32, AMDIL::NEGATE_i32, AMDIL::MAX_i32, AMDIL::NEGATE_i32,
AMDIL::MAX_i32, AMDIL::UDIV_i32, AMDIL::NEGATE_i32, AMDIL::NEGATE_i32,
AMDIL::MAX_i32, AMDIL::NEGATE_i32, AMDIL::MAX_i32, AMDIL::UDIV_i32,
AMDIL::CMOVLOG_i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32,
MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32,
MVT::i32);
}


When it should be transformed into:
SDNode *Emit_29(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2,
unsigned Opc3, unsigned Opc4, unsigned Opc5, unsigned Opc6, unsigned Opc7,
unsigned Opc8, unsigned Opc9, unsigned Opc10, unsigned Opc11, unsigned Opc12,
unsigned Opc13, unsigned Opc14, MVT VT0, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
MVT VT5, MVT VT6, MVT VT7, MVT VT8, MVT VT9, MVT VT10, MVT VT11, MVT VT12, MVT
VT13, MVT VT14) DISABLE_INLINE {
  SDValue N0 = N.getOperand(0);
  SDValue N1 = N.getOperand(1);
  AddToISelQueue(N0);
  AddToISelQueue(N1);
  SDValue Tmp2(CurDAG->getTargetNode(Opc0, VT0, N0, N1), 0);
  SDValue Tmp3 = CurDAG->getTargetConstant(0x80000000ULL, MVT::i32);
  SDValue Tmp4(CurDAG->getTargetNode(Opc1, VT1, Tmp3), 0);
  SDValue Tmp5(CurDAG->getTargetNode(Opc2, VT2, Tmp2, Tmp4), 0);
  AddToISelQueue(N0);
  AddToISelQueue(N0);
  SDValue Tmp8(CurDAG->getTargetNode(Opc3, VT3, N0), 0);
  SDValue Tmp9(CurDAG->getTargetNode(Opc4, VT4, N0, Tmp8), 0);
  AddToISelQueue(N1);
  AddToISelQueue(N1);
  SDValue Tmp12(CurDAG->getTargetNode(Opc5, VT5, N1), 0);
  SDValue Tmp13(CurDAG->getTargetNode(Opc6, VT6, N1, Tmp12), 0);
  SDValue Tmp14(CurDAG->getTargetNode(Opc7, VT7, Tmp9, Tmp13), 0);
  SDValue Tmp15(CurDAG->getTargetNode(Opc8, VT8, Tmp14), 0);
  AddToISelQueue(N0);
  AddToISelQueue(N0);
  SDValue Tmp18(CurDAG->getTargetNode(Opc9, VT9, N0), 0);
  SDValue Tmp19(CurDAG->getTargetNode(Opc10, VT10, N0, Tmp18), 0);
  AddToISelQueue(N1);
  AddToISelQueue(N1);
  SDValue Tmp22(CurDAG->getTargetNode(Opc11, VT11, N1), 0);
  SDValue Tmp23(CurDAG->getTargetNode(Opc12, VT12, N1, Tmp22), 0);
  SDValue Tmp24(CurDAG->getTargetNode(Opc13, VT13, Tmp19, Tmp23), 0);
  return CurDAG->SelectNodeTo(N.getNode(), Opc14, VT14, Tmp5, Tmp15, Tmp24);
}
SDNode *Select_ISD_SDIV_i32(const SDValue &N) {
  return Emit_29(N, AMDIL::BINARY_XOR_i32, AMDIL::LOADCONST_i32,
AMDIL::BINARY_AND_i32, AMDIL::NEGATE_i32, AMDIL::MAX_i32, AMDIL::NEGATE_i32,
AMDIL::MAX_i32, AMDIL::UDIV_i32, AMDIL::NEGATE_i32, AMDIL::NEGATE_i32,
AMDIL::MAX_i32, AMDIL::NEGATE_i32, AMDIL::MAX_i32, AMDIL::UDIV_i32,
AMDIL::CMOVLOG_i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32,
MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32, MVT::i32,
MVT::i32);
}

The problem is the TargetConstant is generated incorrectly.


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