[LLVMbugs] [Bug 3473] New: need load/store merging in dag combine
bugzilla-daemon at cs.uiuc.edu
bugzilla-daemon at cs.uiuc.edu
Tue Feb 3 10:38:48 PST 2009
http://llvm.org/bugs/show_bug.cgi?id=3473
Summary: need load/store merging in dag combine
Product: libraries
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Keywords: code-quality
Severity: normal
Priority: P2
Component: Common Code Generator Code
AssignedTo: unassignedbugs at nondot.org
ReportedBy: clattner at apple.com
CC: llvmbugs at cs.uiuc.edu
This example:
struct s { short a, b, c, d; };
struct s foo(struct s x) {
return x;
}
compiles into:
$ llvm-gcc t.c -S -o - -O3 -fomit-frame-pointer -m32
foo:
movzwl 6(%esp), %ecx
shll $16, %ecx
movzwl 4(%esp), %eax
orl %ecx, %eax
movzwl 10(%esp), %ecx
shll $16, %ecx
movzwl 8(%esp), %edx
orl %ecx, %edx
ret
This is because the struct is passed with by-val, but then reassembled into an
i64 for returning.
%struct.s = type { i16, i16, i16, i16 }
define i64 @foo(%struct.s* nocapture byval align 4 %x) nounwind readonly {
entry:
%0 = getelementptr %struct.s* %x, i32 0, i32 0 ; <i16*>
[#uses=1]
%1 = load i16* %0, align 2 ; <i16> [#uses=1]
%2 = getelementptr %struct.s* %x, i32 0, i32 1 ; <i16*>
[#uses=1]
%3 = load i16* %2, align 2 ; <i16> [#uses=1]
%4 = getelementptr %struct.s* %x, i32 0, i32 2 ; <i16*>
[#uses=1]
%5 = load i16* %4, align 2 ; <i16> [#uses=1]
%6 = getelementptr %struct.s* %x, i32 0, i32 3 ; <i16*>
[#uses=1]
%7 = load i16* %6, align 2 ; <i16> [#uses=1]
%8 = zext i16 %1 to i64 ; <i64> [#uses=1]
%9 = zext i16 %3 to i64 ; <i64> [#uses=1]
%10 = shl i64 %9, 16 ; <i64> [#uses=1]
%11 = zext i16 %5 to i64 ; <i64> [#uses=1]
%12 = shl i64 %11, 32 ; <i64> [#uses=1]
%13 = zext i16 %7 to i64 ; <i64> [#uses=1]
%14 = shl i64 %13, 48 ; <i64> [#uses=1]
%15 = or i64 %10, %8 ; <i64> [#uses=1]
%16 = or i64 %15, %12 ; <i64> [#uses=1]
%17 = or i64 %16, %14 ; <i64> [#uses=1]
ret i64 %17
}
The code generator should merge the small loads (and similar cases with stores)
to avoid this packing logic. gcc compiles this to:
_foo:
movl 4(%esp), %eax
movl 8(%esp), %edx
ret
--
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