[LLVMbugs] [Bug 3460] New: Failed assertion when handling LDR_PRE

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=3460

           Summary: Failed assertion when handling LDR_PRE
           Product: libraries
           Version: 2.4
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P2
         Component: Backend: ARM
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: thebohemian at gmx.net
                CC: llvmbugs at cs.uiuc.edu


I am experiencing a failed assertion when the LDR_PRE instruction is handled by
the JIT compiler:

llvm-2.4-r0/llvm-2.4/include/llvm/CodeGen/MachineOperand.h:251: int64_t
llvm::MachineOperand::getImm() const: Assertion `isImm() && "Wrong
MachineOperand accessor"' failed.

I don't have much experience with the ARM ISA and how LLVM creates the
instructions but I see that some expectation is not met:

The variables MO2 and MO3 in the method
ARMCodeEmitter::getAddrMode2InstrBinary() have the following values when the
problem occurs:

(gdb) p $mo2 = $21
$23 = {OpKind = llvm::MachineOperand::MO_Register, IsDef = false, 
  IsImp = false, IsKill = false, IsDead = false, IsEarlyClobber = false, 
  SubReg = 0 '\0', ParentMI = 0xc971c, Contents = {MBB = 0x18, CFP = 0x18, 
    ImmVal = 3686284530810904, Reg = {RegNo = 24, Prev = 0xd18a8, 
      Next = 0xd0e58}, OffsetedInfo = {Val = {Index = 24, 
        SymbolName = 0x18 <Address 0x18 out of bounds>, GV = 0x18}, 
      Offset = 858280}}}
(gdb) p $mo3 = $22
$24 = {OpKind = llvm::MachineOperand::MO_Register, IsDef = false, 
  IsImp = false, IsKill = false, IsDead = false, IsEarlyClobber = false, 
  SubReg = 0 '\0', ParentMI = 0xc971c, Contents = {MBB = 0x0, CFP = 0x0, 
    ImmVal = 3675529932701696, Reg = {RegNo = 0, Prev = 0xd0ee0, 
      Next = 0xd0e20}, OffsetedInfo = {Val = {Index = 0, SymbolName = 0x0, 
        GV = 0x0}, Offset = 855776}}}

When this code is executed:
 Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
             ARMII::U_BitShift);

MO3.getImm() gets called which triggers the assertion because MO3 is of the
"MO_Register" type.

What I don't know here is:
Is it wrong that MO3 is of type "MO_Register" or is it wrong that the code does
not expect it and unconditionally treats it as if it has the "MO_Immediate"
type.

Perhaps the whole issue is dead easy to solve for someone with experience in
this field. If not it would help me if you can answer me the question above.
Then I can continue searching for the reason of the problem.


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