[LLVMbugs] [Bug 2829] New: llvm.memory. barrier fails to produce write-before-read fence (mfence)

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=2829

           Summary: llvm.memory.barrier fails to produce write-before-read
                    fence (mfence)
           Product: new-bugs
           Version: unspecified
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P2
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: luked at cs.rochester.edu
                CC: llvmbugs at cs.uiuc.edu


The x86 allows load bypassing as per
http://www.intel.com/products/processor/manuals/318147.pdf, and provides the
sse2 "mfence" instruction as a write-before-read fence.

When the "ls" parameter to llvm.memory.barrier is true, llc should emit the
mfence (or some equivalent smarter thing, like an xchg or other locked
instruction if it's already in the instruction sequence). Currently building
the supplied bitcode with "llc -mattr=+sse2 -f -o test.s test.bc" fails to
insert that fence.

This appears to be caused by the 5th parameter to llvm.memory.barrier. Any time
it is false it suppresses the fence. The fifth parameter is very poorly
documented, so I'm not 100% sure if the problem is a documentation bug, or a
bug in the code.

The llvm.memory.barrier is generated by a __sync_synchronize() intrinsic in
llvm-gcc. It could be that the intrinsic should emit the barrier with the 5th
parameter as true, and the documentation needs to be changed.

This also may be related to the gcc bug
http://gcc.gnu.org/ml/gcc-bugs/2008-07/msg01046.html.

Luke


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