[LLVMbugs] [Bug 2616] [CellSPU] Code generation failure
bugzilla-daemon at cs.uiuc.edu
bugzilla-daemon at cs.uiuc.edu
Fri Oct 31 13:58:12 PDT 2008
http://llvm.org/bugs/show_bug.cgi?id=2616
Scott Michel <scooter.phd at gmail.com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|REOPENED |RESOLVED
Resolution| |WORKSFORME
--- Comment #4 from Scott Michel <scooter.phd at gmail.com> 2008-10-31 15:58:10 ---
I just tested this with "llc -march=cellspu -o - zzz.bc" (where zzz.ll has the
example code in the initial bug report, which was then llvm-as-ed to zzz.bc).
Other than the ellipsis that indicates a vararg function, llc accepts it just
fine and generates code w/o an assert.
Heisenbug caused by something else other than the backend?
If you take out the ellipsis, i.e.:
; ModuleID = 't0038.ubc'
define i32 @main() {
entry:
%retval = alloca i32 ; <i32*> [#uses=2]
store i32 0, i32* %retval
%i = alloca i32 ; <i32*> [#uses=0]
br label %return
return: ; preds = %entry
load i32* %retval ; <i32>:0 [#uses=1]
ret i32 %0
}
llc produces the following (it isn't the greatest code produced, but it is
assert-free):
.text
.align 3
.global main
.type main, @function
main:
stqd $lr, 16($sp)
stqd $sp, -64($sp)
ai $sp, $sp, -64
lqd $3, 0($sp)
cwd $4, 0($sp)
il $5, 0
shufb $3, $5, $3, $4
stqd $3, 0($sp)
.LBB1_1: # return
lqd $3, 0($sp)
rotqby $3, $3, $sp
lqd $lr, 80($sp)
ai $sp, $sp, 64
bi $lr
.size main,.-main
.ident "(llvm 2.2+) STI CBEA Cell SPU backend"
Note: This is similar to what would be produced by llc with the ellipsis, but
without the spillage of 48 registers to the stack:
.text
.align 3
.global main
.type main, @function
main:
stqd $lr, 16($sp)
stqd $sp, -64($sp)
ai $sp, $sp, -64
stqd $79, 1312($sp)
stqd $78, 1296($sp)
stqd $77, 1280($sp)
stqd $76, 1264($sp)
stqd $75, 1248($sp)
stqd $74, 1232($sp)
stqd $73, 1216($sp)
stqd $72, 1200($sp)
stqd $71, 1184($sp)
stqd $70, 1168($sp)
stqd $69, 1152($sp)
stqd $68, 1136($sp)
stqd $67, 1120($sp)
stqd $66, 1104($sp)
stqd $65, 1088($sp)
stqd $64, 1072($sp)
stqd $63, 1056($sp)
stqd $62, 1040($sp)
stqd $61, 1024($sp)
stqd $60, 1008($sp)
stqd $59, 992($sp)
stqd $58, 976($sp)
stqd $57, 960($sp)
stqd $56, 944($sp)
stqd $55, 928($sp)
stqd $54, 912($sp)
stqd $53, 896($sp)
stqd $52, 880($sp)
stqd $51, 864($sp)
stqd $50, 848($sp)
stqd $49, 832($sp)
stqd $48, 816($sp)
stqd $47, 800($sp)
stqd $46, 784($sp)
stqd $45, 768($sp)
stqd $44, 752($sp)
stqd $43, 736($sp)
stqd $42, 720($sp)
stqd $41, 704($sp)
stqd $40, 688($sp)
stqd $39, 672($sp)
stqd $38, 656($sp)
stqd $37, 640($sp)
stqd $36, 624($sp)
stqd $35, 608($sp)
stqd $34, 592($sp)
stqd $33, 576($sp)
stqd $32, 560($sp)
stqd $31, 544($sp)
stqd $30, 528($sp)
stqd $29, 512($sp)
stqd $28, 496($sp)
stqd $27, 480($sp)
stqd $26, 464($sp)
stqd $25, 448($sp)
stqd $24, 432($sp)
stqd $23, 416($sp)
stqd $22, 400($sp)
stqd $21, 384($sp)
stqd $20, 368($sp)
stqd $19, 352($sp)
stqd $18, 336($sp)
stqd $17, 320($sp)
stqd $16, 304($sp)
stqd $15, 288($sp)
stqd $14, 272($sp)
stqd $13, 256($sp)
stqd $12, 240($sp)
stqd $11, 224($sp)
stqd $10, 208($sp)
stqd $9, 192($sp)
stqd $8, 176($sp)
stqd $7, 160($sp)
stqd $6, 144($sp)
stqd $5, 128($sp)
stqd $4, 112($sp)
stqd $3, 96($sp)
lqd $3, 0($sp)
cwd $4, 0($sp)
il $5, 0
shufb $3, $5, $3, $4
stqd $3, 0($sp)
.LBB1_1: # return
lqd $3, 0($sp)
rotqby $3, $3, $sp
lqd $lr, 80($sp)
ai $sp, $sp, 64
bi $lr
.size main,.-main
.ident "(llvm 2.2+) STI CBEA Cell SPU backend"
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