[LLVMbugs] [Bug 2313] New: ARM: Rd and Rm registers should be different in MUL on ARMv5
bugzilla-daemon at cs.uiuc.edu
bugzilla-daemon at cs.uiuc.edu
Sun May 11 09:42:09 PDT 2008
http://llvm.org/bugs/show_bug.cgi?id=2313
Summary: ARM: Rd and Rm registers should be different in MUL on
ARMv5
Product: libraries
Version: trunk
Platform: All
OS/Version: All
Status: NEW
Severity: normal
Priority: P2
Component: Backend: ARM
AssignedTo: unassignedbugs at nondot.org
ReportedBy: jhw at conjury.org
CC: llvmbugs at cs.uiuc.edu
The ARMv6 CPU allows the Rd and Rm registers to be the same in the MUL
instruction, but this isn't allowed on, for example the ARMv5 CPU. As a
result, GAS will issue complaints about LLVM-generated ARM code. Here's a
sample:
sample.s: Assembler messages:
sample.s:59: Rd and Rm should be different in mul
sample.s:63: Rd and Rm should be different in mul
sample.s:104: Rd and Rm should be different in mul
sample.s:108: Rd and Rm should be different in mul
These messages came from assembling the following LLVM-generated code:
.globl rand_r
.align 2
rand_r:
ldr r3, [r0]
ldr r2, .LCPI3_0
cmp r3, #0
moveq r3, r2
ldr r2, .LCPI3_1
umull r1, r2, r3, r2
sub r1, r3, r2
add r2, r2, r1, lsr #1
mov r2, r2, lsr #16
mov r1, #197, 30 @ 788
orr r1, r1, #2, 22 @ 2048
mul r1, r2, r1
ldr r12, .LCPI3_2
mul r2, r2, r12 ; <------------ Here is line 59.
sub r3, r3, r2
mov r2, #167
orr r2, r2, #65, 24 @ 16640
mul r3, r3, r2 ; <------------ Here is line 63.
sub r3, r3, r1
sub r2, r3, #6, 2 @ -2147483647
cmp r3, #0
movge r2, r3
str r2, [r0]
bic r0, r2, #2, 2 @ -2147483648
bx lr
.LBB3_1:
.LCPI3_0:
.long 123459876
.LCPI3_1:
.long 110892733
.LCPI3_2:
.long 127773
Yes, this really is the rand_r() function from the standard C library.
This code is fine for ARMv6, but it doesn't work for the ARMv5 CPU I'm playing
with, so here is the bug report.
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