[LLVMbugs] [Bug 1993] New: Variants are inappropriately pruned

bugzilla-daemon at cs.uiuc.edu bugzilla-daemon at cs.uiuc.edu
Wed Feb 6 17:20:55 PST 2008


           Summary: Variants are inappropriately pruned
           Product: tools
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: major
          Priority: P2
         Component: TableGen
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: scottm at aero.org
                CC: llvmbugs at cs.uiuc.edu

Created an attachment (id=1383)
 --> (http://llvm.org/bugs/attachment.cgi?id=1383)
Testcase to demonstrate variant pattern pruning bug

Consider the following instruction patterns:

class SELBVecInst<ValueType vectype>:
  SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
           [(set (vectype VECREG:$rT),
                 (or (and (vectype VECREG:$rA), (vectype VECREG:$rC)),
                     (and (vectype VECREG:$rB), (vnot (vectype

def SELBv16i8: SELBVecInst<v16i8>;

class SPUVecInst2<ValueType vectype>:
  SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
           [(set (vectype VECREG:$rT),
                 (or (and (vectype VECREG:$rA), (vnot (vectype VECREG:$rC))),
                     (and (vectype VECREG:$rB), (vectype VECREG:$rC))))]>;

def SELBv16i8_2 : SPUVecInst2<v16i8>;

tblgen creates 8 variants for SELBv16i8 and 8 variants for SELBv16i8_v2. The
problem revolves around matching this input:

(or                               N
  (and                            N0
     VECREG:$rA,                  N00
     (xor                         N01
       (build_vector <-1, ...>),  N011, N0110
       VECREG:$rC))               N010
    (and                          N1
       VECREG:$rC,                N10
       VECREG:$rB))               N11

Using tblgen's labeling in the instruction selector, the operands need to match
as follows:

  N.getOpcode() == ISD::OR
  N0.getOpcode() == ISD::AND
  N1.getOpcode() == ISD::AND
  N01.getOpcode() == ISD::XOR
  N011.getOpcode() == BUILD_VECTOR
  N010 == N10

However, this particular instruction matching sequence is never generated
because the pattern to match is considered isomorphic to another variant
pattern (see attached output from tblgen).

Not sure how to fix CodeGenDAGPatterns.cpp or isIsomorphicTo() so that all
variant patterns are actually matched...

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