[LLVMbugs] [Bug 1765] New: condition register bits and registers confused

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=1765

           Summary: condition register bits and registers confused
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P2
         Component: Backend: PowerPC
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: nicholas at mxc.ca
                CC: llvmbugs at cs.uiuc.edu


The PPC backend currently emits code that doesn't distinguish between CR6 and
bit 6 (being a bit in CR1). This breaks PPC/Linux where "creqv 6, 6, 6" is
thought by the backend to be clobbering CR6 instead of CR1EQ.

Often the problem manifests in code like:
  creqv 2, 2, 2
  mr 6, 2
  bl somevararg1
  mr 6, 2
  bl somevararg2

and this crops up in 2005-03-07-VarArgs.c.

I'm not sure what the correct fix looks like. I tried modelling each CR-bit as
an i1 subreg of the CR and made a total mess of things. (I can attach the patch
if anyone wants it.)


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