[LLVMbugs] [Bug 1272] NEW: Assertion failed generating code (ScheduleDAG.cpp:377)

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=1272

           Summary: Assertion failed generating code (ScheduleDAG.cpp:377)
           Product: new-bugs
           Version: unspecified
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P2
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: nipo at ssji.net


I'm rather new to LLVM and trying to compile some C++ software I already got.
llvm-g++ produced a bytecode file happily, but I get an assertion failure when
translating the bytecode to x86 machine code, either through lli or llc.

Assertion failure is:
llc: /dsk/l1/compilation/cvs/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:378:
void llvm::ScheduleDAG::AddOperand(llvm::MachineInstr*, llvm::SDOperand,
unsigned int, const llvm::TargetInstrDescriptor*, llvm::DenseMap<llvm::SDNode*,
unsigned int, llvm::DenseMapKeyInfo<llvm::SDNode*> >&): Assertion
`RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of
use don't agree!"' failed.
llc((anonymous namespace)::PrintStackTrace()+0x1a)[0x88dfe50]
llc((anonymous namespace)::SignalHandler(int)+0x110)[0x88e0114]
[0xb7f4e420]
/lib/libc.so.6(abort+0x109)[0xb7d17c69]
/lib/libc.so.6(__assert_fail+0xfc)[0xb7d0feac]
llc(llvm::ScheduleDAG::AddOperand(llvm::MachineInstr*, llvm::SDOperand, unsigned
int, llvm::TargetInstrDescriptor const*, llvm::DenseMap<llvm::SDNode*, unsigned
int, llvm::DenseMapKeyInfo<llvm::SDNode*> >&)+0x7c7)[0x86d2dff]
llc(llvm::ScheduleDAG::EmitNode(llvm::SDNode*, llvm::DenseMap<llvm::SDNode*,
unsigned int, llvm::DenseMapKeyInfo<llvm::SDNode*> >&)+0x28d)[0x86d3095]
llc(llvm::ScheduleDAG::EmitSchedule()+0x2a8)[0x86d3c72]
llc[0x8640e51]
llc(llvm::ScheduleDAG::Run()+0x94)[0x86d1a4c]
llc(llvm::SelectionDAGISel::ScheduleAndEmitDAG(llvm::SelectionDAG&)+0x73)[0x8662def]
llc[0x850f31e]
llc(llvm::SelectionDAGISel::CodeGenAndEmitDAG(llvm::SelectionDAG&)+0x137)[0x8662f49]
llc(llvm::SelectionDAGISel::SelectBasicBlock(llvm::BasicBlock*,
llvm::MachineFunction&, llvm::FunctionLoweringInfo&)+0xad)[0x8677dad]
llc(llvm::SelectionDAGISel::runOnFunction(llvm::Function&)+0x5cf)[0x867940f]
llc[0x853fcf5]
llc(llvm::FPPassManager::runOnFunction(llvm::Function&)+0x13a)[0x886d506]
llc(llvm::FunctionPassManagerImpl::run(llvm::Function&)+0x6e)[0x886d788]
llc(llvm::FunctionPassManager::run(llvm::Function&)+0x88)[0x886d848]
llc(main+0xbc3)[0x83d8445]
/lib/libc.so.6(__libc_start_main+0xd8)[0xb7d03878]
llc(__gxx_personality_v0+0x179)[0x83d67e1]
Aborted

Putting a bp in gdb just before the assertion, I get:

Breakpoint 3, llvm::ScheduleDAG::AddOperand (this=0x92affc8, MI=0x8d42f00,
Op={Val = 0x92af680, ResNo = 0}, IIOpNum=4, II=0x894cdc0, VRBaseMap=@0xbfe67e50)
    at /dsk/l1/compilation/cvs/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:377
377           assert(RegMap->getRegClass(VReg) == RC &&
3: RC = (const llvm::TargetRegisterClass *) 0x8a03e80
1: this->RegMap->getRegClass (VReg) = (const llvm::TargetRegisterClass *) 0x8a04080

Dumping some variables around:

(gdb) print *RC
$1 = {_vptr.TargetRegisterClass = 0x895d988, ID = 2, isSubClass = false, VTs =
0x8959200, SubClasses = 0x8959208, SuperClasses = 0x895920c, RegSize = 8,
Alignment = 8, RegsBegin = 0x89591c0, 
  RegsEnd = 0x8959200}
(gdb) print *this->RegMap->getRegClass (VReg) 
$2 = {_vptr.TargetRegisterClass = 0x895d910, ID = 10, isSubClass = false, VTs =
0x8958da0, SubClasses = 0x8958da8, SuperClasses = 0x8958dac, RegSize = 8,
Alignment = 4, RegsBegin = 0x8958d80, 
  RegsEnd = 0x8958da0}
(gdb) print VReg
$3 = 1069
(gdb) print Op
$4 = {Val = 0x92af680, ResNo = 0}
(gdb) print *MI
$5 = {TID = 0x894cdc0, NumImplicitOps = 0, Operands =
{<std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >> = {
      _M_impl = {<std::allocator<llvm::MachineOperand>> =
{<__gnu_cxx::new_allocator<llvm::MachineOperand>> = {<No data fields>}, <No data
fields>}, _M_start = 0x92b04e8, _M_finish = 0x92b0538, 
        _M_end_of_storage = 0x92b0538}}, <No data fields>}, prev = 0x0, next =
0x928ec01, parent = 0x0}
(gdb) print IIOpNum
$6 = 4
(gdb) print (void)Op.Val->dump(&DAG)  
0x92af680: f64,ch,flag = CopyFromReg 0x92af7e0, 0x92af538, 0x92af7e0:1
$7 = void



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