[LLVMbugs] [Bug 1184] NEW: ScheduleDAG.cpp patch: error message more meaningful.

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=1184

           Summary: ScheduleDAG.cpp patch: error message more meaningful.
           Product: libraries
           Version: trunk
          Platform: All
        OS/Version: Linux
            Status: NEW
          Severity: enhancement
          Priority: P2
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: scottm at aero.org


Small patch to make tracking down (self-inflicted) bugs easier when the 
scheduler barfs. The assert() wasn't really helpful at all. At least this patch 
tells you which instruction and operand to go look at.

(Note: In the end, yes, it was my fault, but this patch actually helped.)

Index: lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp    (revision 522)
+++ lib/CodeGen/SelectionDAG/ScheduleDAG.cpp    (working copy)
@@ -301,9 +301,20 @@
     if (II) {
       const TargetRegisterClass *RC =
                           getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+      const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
       assert(RC && "Don't have operand info for this instruction!");
-      assert(RegMap->getRegClass(VReg) == RC &&
-             "Register class of operand and regclass of use don't agree!");
+      if (VRC != RC) {
+       cerr << "Register class of operand and regclass of use don't agree!\n";
+       cerr << "Operand = " << IIOpNum << "\n";
+       cerr << "Op->Val = "; Op.Val->dump(0); cerr << "\n";
+       cerr << "MI = "; MI->print(cerr);
+       cerr << "VReg = " << VReg << "\n";
+       cerr << "VReg RegClass     size = " << VRC->getSize()
+            << ", align = " << VRC->getAlignment() << "\n";
+       cerr << "Expected RegClass size = " << RC->getSize()
+            << ", align = " << RC->getAlignment() << "\n";
+       abort();
+      }
     }
   } else if (ConstantSDNode *C =
              dyn_cast<ConstantSDNode>(Op)) {



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