[LLVMbugs] [Bug 770] NEW: Permit coallescing of registers in subset register classes

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=770

           Summary: Permit coallescing of registers in subset register
                    classes
           Product: libraries
           Version: 1.0
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: enhancement
          Priority: P2
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: sabre at nondot.org


PowerPC has two very similar, but different, register classes.  One contains [R1..R31] and one contains 
[R0..R31].

Some instructions can have operands from the full [R0..R31] range, while others do not allow R0.  
Currently, we just never allocate R0 to any instruction, though it can often profitably be used (the 
instructions which cannot use R0 are rare).

It would be nice to have two explicit register classes for these registers, and have the instructions 
explicit about what they permit.  We can do this today, with two problems:

1. We would have to implement copy instructions for moving registers back and forth between the 
register files, A->A, A->B, B->A, B->B.  This sucks.

2. The register allocator will not coallesce the copies away, leading to really bad code.


The solution to both of these is to teach the code generate about subset register classes.  In particular, 
we should be able to say that any instruction that allows [R0..R31] implicitly permits the subset register 
class [R1..R31] to be used as an operand.  This solves issue #1, because we would just have to define 
copy as [R0..R31] -> [R0..R31].

Once we have this in place, we can teach the coallescer to coallesce these two register classes.  The 
coallesce a [R0..R31] vreg with an [R1..R31] vreg, we produce a new vreg which is in the [R1..R31] class.  
This is guaranteed safe and should be reasonably easy to do.

-Chris



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