[LLVMbugs] [Bug 566] NEW: Memory Mapped I/O Intrinsics do not fence memory

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=566

           Summary: Memory Mapped I/O Intrinsics do not fence memory
           Product: libraries
           Version: 1.5
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: minor
          Priority: P2
         Component: Backend: X86
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: criswell at uiuc.edu


According to the design in the language reference manual, the LLVM readio and
writeio intrinsics should strongly order I/O memory accesses.

However, the current implementation lowers these intrinsics to volatile loads
and stores on ix86.  These loads and stores may or may not be properly ordered,
depending on the processor on which they run.

The correct solution is not obvious.  Certain fencing instructions are not found
on older Pentium processors, and we will need a general fencing model for SMP
systems anyway.  Such a design has not been discussed, though, as far as I know.



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