[LLVMbugs] [Bug 519] NEW: [x86] instruction opcodes have inconsistent names

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=519

           Summary: [x86] instruction opcodes have inconsistent names
           Product: libraries
           Version: trunk
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: enhancement
          Priority: P2
         Component: X86 Backend
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: brukman+bugs at uiuc.edu


X86 backend needs to differentiate instruction operands based on their width in
bits, so it has opcodes such as IMUL16rmi8 (imul, 16-bit register, 16-bit
memory, 8-bit immediate).  However, that's inconsistent: for the first two (rm),
the width comes BEFORE the 'rm' specifier, but the width for the immediate (8)
comes AFTER the 'i' specifier.

One solution would be to standardize on having the numbers ALWAYS BEFORE the
type specifiers, so this opcode would become IMUL16rm8i.  This change would
affect the entire x86 backend, and the documentation that mentions any opcodes
explicitly would need to change as well (one example is docs/CodeGenerator.html).



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